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Method and apparatus for fine-grained program interruption control

IP.com Disclosure Number: IPCOM000011891D
Original Publication Date: 2003-Mar-21
Included in the Prior Art Database: 2003-Mar-21
Document File: 1 page(s) / 40K

Publishing Venue

IBM

Abstract

The invention discloses a method for fine-grained program interruption control of asynchronous events. According to the disclosed method, an instruction set architecture is enhanced by an indicator in the instruction word to indicate whether an interrupt can be taken after the processing of said instruction. In an alternative embodiment, an asynchronous interrupt can be taken before the processing of said instruction.

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YOR820020140 Louis J Percello/Watson/IBM Michael Gschwind

Method and apparatus for fine -grained program interruption control

In programs, there may be a need to prevent the occurrence of asynchronous program interruptions, e.g., by external exception or interrupt conditions. An example of such a need is in dynamically generated code in a binary translation and/or optimization system, where the internal program state is only consistent at some program points. To prevent occurrence of program executions which cannot occur according to the original program specification in compliance with arhcitecture documents, the program should only be interrupted when the state is consistent with the original program specification. Another example of the need to prevent external interruptions can be in critical program regions, e.g., those executing under time-critical constraints, or operating on critical data sections.

In current art, the exclusion of external asynchronous interrupts and exceptions is achieved by writing a machine state register, or executing a "disable asynchronous interrupt" instruction. However, this can be expensive due to the need to execute additional instructions, in particular, if the ability to take interrupts needs to be enabled and disabled at fine granularity intervals.

According to the disclosed method, an instruction set architecture is enhanced by an indicator in t...