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Method for a selective hourglass solder joint array

IP.com Disclosure Number: IPCOM000011934D
Publication Date: 2003-Mar-26
Document File: 7 page(s) / 601K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for a selective hourglass solder joint array. Benefits include improved functionality, improved performance, and improved reliability.

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Method for a selective hourglass solder joint array

Disclosed is a method for a selective hourglass solder joint array. Benefits include improved functionality, improved performance, and improved reliability.

Background

              Solder-joint fatigue failure occurs at the solder ball-to-component and printed circuit board (PCB) interface due to high stress during reliability testing in temperature cycling and shock-and-vibration test. For example, high thermal/mechanical stress is underneath the silicon die due to the die shadow effect of high coefficient of thermal (CTE) mismatch between the silicon die and the component substrate package.

              Conventional solutions include:                                                                                                               

•             Larger solder ball to increase solder-joint standoff because higher standoff minimizes stress at the solder ball-to-component or PCB pad interface

•             Metal defined (MD) pad to minimize the pinching effect from the solder mask coating edge on the solder ball, especially at the high stress concentration interface

•             90/10 Pb/Sn solder balls with eutectic Pb-Sn solder paste as the interconnection on the component-to-PCB interface

•             Control of solder resist opening ratio between motherboard vs. component pad openings to control the solder ball to pad interface stress distribution.

General description

              The disclosed method is a selective hourglass solder joint array for reliability enhancement at a high-stress concentration area. The ball grid array (BGA) acts as a spacer to maintain the solder joint’s standoff. An hourglass solder joint array is produced on unplugged via-in-pads (VIPs) on PCB pads. Ball-grid solder joints are produced on non-VIP locations.

              During reflow soldering, solder from the solder ball flows into unplugged via-holes at the VIP pads to form hourglass solder joints. Non-VIP pads remain as barrel-shaped solder joints.

              The key elements of the method include:

•             Internal diameter for unplugged BGA VIP pad is ~6-7 mils on a round-shaped BGA pad diameter at 20 mils.

•             BGA VIP via-hole cylindrical sidewall is coated with ~1-mils thick Cu plating.

•             The location and distribution of the unplugged VIP and non-VIP BGA pad should be optimized to ensure balance collapse and the high-stress concentration location.

•             SMT reflow process is optimized to ensure sufficient solder migrates into the via-hole.

Advantages

              The disclosed method provides advantages, including:

•             Improved functionality due to the formation of selective hourglass-shaped solder joints on VIP pads at high-stress locations and barrel-shaped solder joints on non-VIP (flat) pads

•             Improved performance due to improved the routing density by using VIP

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