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Method for embedded Cu wire in multicoated passive component

IP.com Disclosure Number: IPCOM000011943D
Publication Date: 2003-Mar-26
Document File: 6 page(s) / 441K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for embedded copper (Cu) wire in multicoated passive component. Benefits include improved reliability, improved performance, and improved support for future technology.

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Method for embedded Cu wire in multicoated passive component

Disclosed is a method for embedded copper (Cu) wire in multicoated passive component. Benefits include improved reliability, improved performance, and improved support for future technology.

Background

        � � � � � Resistor/capacitor pack (R-pack) solder-joint fatigue cracking causes electrical open failure after temperature cycling testing. A top view of the R-pack indicates solder fatigue typically occurs at the four-corners solder fillet due to high shear stress from the distance-to-neutral-point (DNP) effect (see Figure 1). The dotted red line indicates the cross-section direction. A high-magnification optical image shows a solder fatigue crack path indicated in a blue color arrow (see Figure 2). The image also indicates a single coating layer on a resistor pack terminal. Photos show a passive crack at the terminals under the die shadow of a processor (see Figure 3).

        � � � � � The cracking is attributed to the coefficient of thermal expansion (CTE) mismatch coupled with the lower pad area (increase in stress). The cracking path is closely matched with the stress-strain micrograph.

        � � � � � A conventional method to resolve resistor-pack solder fatigue failure is to enlarge the R-pack terminal coating area to increase the solder joint contact area. Another method is to utilize a larger Cu pad area on the PCB for larger terminal solder joint formation. However, these methods do not totally resolve R-pack fatigue because localized mechanical stress enhances solder fatigue.

        � � � � �

        � � � � � The conventional terminal coating layer is ~1.5 to 2.0 mils.

General description

        � � � � � The disclosed method is embedded Cu wire in multicoated passive component. Cu wire with a J-shape is embedded on a passive resistor pack terminal. This process step is followed by a solder coating process. The J-shape Cu wires block fatigue cracking of the R-pack and improve the solder fillet stand off that reduces the in-plane shear stress, enhancing the solder joint reliability.

        � � � � � The key elements of the method include:

•        � � � � Cu wire with a J-shape inserted on passive pack’s terminal to block the fatigue crack direction

•        � � � � Solder layer that is coated on top of the wire, embedding it under the coating

•        � � � � Terminal coating height of ~3.0 to 4 mils

•        � � � � Cu wire thickness of ~0.5 to 1.0 mils

•        � � � � Cu wire width of ~0.6 to 0.8 times the terminal...