Browse Prior Art Database

Tool for periodic extraction of multi-level dispatch affinity information

IP.com Disclosure Number: IPCOM000012046D
Original Publication Date: 2003-Apr-03
Included in the Prior Art Database: 2003-Apr-03
Document File: 2 page(s) / 40K

Publishing Venue

IBM

Abstract

Operating system tool for multi-level affinity dispatch monitoring

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Tool for periodic extraction of multi-level dispatch affinity information

Many hardware's today have multiple levels of cache and memory. This invention includes the ability to monitor the execution of programs against cache and memory for all levels of the memory hierarchy simultaneously. To accomplish this, the operating system will keep information on the following items.

At thread creation time, the thread is marked with its "home" node, which reflects the physical memory associated with the threads execution. For each dispatch, the OS will select a thread to run and increment a per-processor count under the following circumstances:

1) This is a new thread, never dispatched
2) This is not a new thread and was last dispatched on a processor which shares L1 cache(s) with the current processor. NOTE: this is equivalent to hardware multi-threading or symmetric multi-threading
3) This is not a new thread and was last dispatched on a processor which does not share L1 cache(s) with the current processor, but shares L2 caches with the current processor.
4) This is not a new thread and was last dispatched on a processor which does not share L1/L2 cache(s) with the current processor, but shares L3 caches with the current processor.
5) This is not a new thread and was last dispatched on a processor which does not share L1/L2/L3/L4 or any other caches with the current processor.
6) The thread is dispatched on a processor which is logically associated with the threads "home"...