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Memory test for embedded systems which is based on a combined hardware and software approach

IP.com Disclosure Number: IPCOM000012075D
Original Publication Date: 2003-May-25
Included in the Prior Art Database: 2003-May-25
Document File: 2 page(s) / 82K

Publishing Venue

Siemens

Related People

Juergen Carstens: CONTACT

Abstract

Most integrated circuits contain embedded memories (e.g. static RAMs). The functionality of these memories has to be verified during the production test in the factory. The memory tests usually write defined data into defined memory locations and read them back afterwards. There are two things to consider when performing the memory test. Firstly the address descrambling has to be performed, since one wants to access one word line after the other and a constantly increasing address does not map directly to continuous word line addressing as the side effect of the address decoder. Secondly the data, which will be written to/ read from the memory test, depends also on the topology of the memory. Depending on the physical layout of the bits in a word line and the possible shorts amongst them a different data word is needed. The problem is that the address descrambling and the required data pattern are different for each memory (i.e. high effort and high risk of wrong implementation). Currently there are two common approaches to implement a memory test. In a hardware BIST (Built In Self Test) a dedicated hardware is used to perform the read/write accesses to the memory. Usually the address descrambling is fixed (inverse function of address decoding), but the data pattern can be programmed. The disadvantage here is that the descrambling can not be corrected in case of a wrong implementation (very likely). A SIST (Software Implemented Self Test) can be performed, if the system contains a microprocessor and if it has access to the memory. The disadvantage here is that the memories often have a different data width compared to the microprocessor, i.e. if the memory has redundant bits in a word line to allow automatic error detection and correction. Therefore data assembly/disassembly by software is required which leads to increased test times.

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© SIEMENS AG 2003 file: ifx_2003J50114.doc page: 1

Memory test for embedded systems which is based on a combined hardware and software approach

Idea: Tommaso Bacigalupo, DE-Munich; Siegfried Lewalter, DE-Munich

Most integrated circuits contain embedded memories (e.g. static RAMs). The functionality of these memories has to be verified during the production test in the factory. The memory tests usually write defined data into defined memory locations and read them back afterwards. There are two things to consider when performing the memory test. Firstly the address descrambling has to be performed, since one wants to access one word line after the other and a constantly increasing address does not map directly to continuous word line addressing as the side effect of the address decoder. Secondly the data, which will be written to/ read from the memory test, depends also on the topology of the memory. Depending on the physical layout of the bits in a word line and the possible shorts amongst them a different data word is needed. The problem is that the address descrambling and the required data pattern are different for each memory (i.e. high effort and high risk of wrong implementation).

Currently there are two common approaches to implement a memory test. In a hardware BIST (Built In Self Test) a dedicated hardware is used to perform the read/write accesses to the memory. Usually the address descrambling is fixed (inverse function of address decoding), but the data pattern can be programmed. The disadvantage here is that the descrambling can not be corrected in case of a wrong implementation (very likely). A SIST (Software Implemented Self Test) can be performed, if the system contains a microprocessor and if it has access to the memory. The disadvantage here is that the memories often have a different data width compared to the microprocessor, i.e. if the memory has redundant bits in a word line to allow automatic error detection and correction. Therefore data assembly/disassembly by software is required which leads to increased test times.

The new idea is to combine the software and the hardware for the memory test. The address descrambling is performed by the software running on the microprocessor: This microprocessor performs the calculation of the address sequence, which has to be applied to the memory: i.e. it reverses the effect of the memory address decoders. This software can be changed easily and thus a wrong implementation can be changed without problems. The write data for the memory will be generated by a programmable pattern generator. This pattern generator can be programmed to support the sequences of well-known memory tests like checkerboard/inverse checkerboard, 14n, marching zero/one etc. It is accompanied by a matching pattern comparator, which checks the read data from the memory. The pattern generator/comparator does support memories of any data width. Thus no data assembly/disassembly is necessary. The flo...