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2-Transistor Flash Memory Cell with Low Operating Voltage and No Read Disturb

IP.com Disclosure Number: IPCOM000012078D
Original Publication Date: 2003-Apr-07
Included in the Prior Art Database: 2003-Apr-07
Document File: 4 page(s) / 161K

Publishing Venue

Motorola

Related People

Jane Yater: AUTHOR [+4]

Abstract

SONOS (Silicon-Oxide-Nitride-Oxide-Silicon) is an attractive non-volatile memory technology due to reduced process complexity, lower program and erase voltages, and improved extrinsic reliability compared to floating gate memory. Low voltage operation of Flash EEPROM memory can be obtained by using a thin film storage device, such as SONOS, with a tunnel oxide thickness in the range of 15-30Å. By splitting the bias between the gate and substrate, the voltages required for program/erase operation can be reduced in magnitude to 3-8V. However, read disturb is a concern for thin film memories due to the thin dielectric films used to achieve fast tunnel erase speeds, [1]. Gate voltages of 2-3V can cause unacceptable charge loss for bitcells in the low Vt state. To eliminate read disturb, no additional electric field should be applied that would cause charge to move out of or into the storage medium. This paper describes a 2-transistor source-select flash memory cell operating in depletion mode that eliminates read disturb. Programming to the high Vt state is achieved through hot carrier injection (HCI) or uniform tunnel operation while erase is obtained through uniform tunneling. Either a common or decoded source design is possible.

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2-Transistor Flash Memory Cell with Low Operating Voltage and No Read Disturb

Jane Yater, Bruce Morton, Erwin Prinz and Craig Swift

Abstract

SONOS (Silicon-Oxide-Nitride-Oxide-Silicon) is an attractive non-volatile memory technology due to reduced process complexity, lower program and erase voltages, and improved extrinsic reliability compared to floating gate memory.� Low voltage operation of Flash EEPROM memory can be obtained by using a thin film storage device, such as SONOS, with a tunnel oxide thickness in the range of 15-30Å.� By splitting the bias between the gate and substrate, the voltages required for program/erase operation can be reduced in magnitude to 3-8V.� However, read disturb is a concern for thin film memories due to the thin dielectric films used to achieve fast tunnel erase speeds, [1]. Gate voltages of 2-3V can cause unacceptable charge loss for bitcells in the low Vt state.� To eliminate read disturb, no additional electric field should be applied that would cause charge to move out of or into the storage medium.� This paper describes a 2-transistor source-select flash memory cell operating in depletion mode that eliminates read disturb.� Programming to the high Vt state is achieved through hot carrier injection (HCI) or uniform tunnel operation while erase is obtained through uniform tunneling.� Either a common or decoded source design is possible.

Body

A schematic of a typical SONOS cell is shown in Figure 1.� The dielectric stack traditionally consists of a bottom, tunnel oxide with a silicon nitride or oxynitride charge storage layer and top blocking oxide. Other materials may be used, such as semiconductor or metal nanocrystals for the charge storage material, or high K dielectrics for charge storage, tunnel or blocking dielectric.� In the cell configuration shown, both program and erase occur by carrier transport across the thin bottom oxide.� Alternatively, by scaling the stack such that the top oxide is thinner than the bottom, tunnel program and erase can occur across the top oxide.� For thin tunnel oxide from 15-30Å, read disturb of the low Vt state can be avoided through appropriate design considerations.� One method [2] utilizes a depleted low Vt state such that there is no disturb for read conditions of Vg = Vs and Vd = Vs + � d due to shielding of any back bias well voltage by the inversion layer.� �

In the invention described here, the SONOS device operates in depletion mode so that read can be accomplished with 0V gate voltage.� To overcome the subsequent problem of column leakage during read, a two-transistor source-select design is utilized [3].� The SONOS cell and select gate transistor (identified as bitcell A) sit in an isolated p-well and can either have a common source or a decoded source, as shown in Figure 2a and 2b, respectively.� � The select gate transistor, with a Vt greater than 0V, will have a different gate oxide and may have different well doping.� Program operation is possible with e...