Browse Prior Art Database

Method of improving leakage current in a MOS transistor

IP.com Disclosure Number: IPCOM000012079D
Original Publication Date: 2003-Apr-07
Included in the Prior Art Database: 2003-Apr-07
Document File: 3 page(s) / 88K

Publishing Venue

Motorola

Related People

Vishnu Khemka: AUTHOR [+5]

Abstract

This publication proposes a novel scheme to improve the leakage current in MOS transistors in deep sub-micron technologies with shallow source/drain implants. The technique is specifically suitable for smart power technologies where, low-voltage CMOS devices are integrated with medium and high-voltage analog devices.

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Method of improving leakage current in a MOS transistor

Vishnu Khemka, Vijay Parthasarathy, Ronghua Zhu,

Amitava Bose, and Todd Roggenbauer

Abstract:        � � � � � � � � This publication proposes a novel scheme to improve the leakage current in MOS transistors in deep sub-micron technologies with shallow source/drain implants. The technique is specifically suitable for smart power technologies where, low-voltage CMOS devices are integrated with medium and high-voltage analog devices.

In deep sub-micron technologies as the feature size and operating voltages are reduced, the off-state leakage current of the MOS transistor becomes very critical. Ultra shallow junction for source/drain formation and use of silicided process aggravate the leakage current issue. Fig.1 illustrates the problem where the self-aligned silicide wraps around the field oxide (shallow trench or LOCOS based isolation). Since the source and drain implants are extremely shallow, this wrapped around silicide can cause a short at the drain to body junction and create undesirable leakage currents in the device characteristics. This leakage current typically shows up in the device characteristics in the medium voltage range that is not a concern for low-voltage CMOS devices. In smart power technologies, however, where deep sub-micron low-voltage CMOS devices are integrated with medium and high-voltage analog MOS devices, it poses a problem which must be solved to realize acceptable device performance.

One straightforward way to eliminate or improve the silicide short across the source/drain to WELL body junction is to make sure...