Browse Prior Art Database

Fabricating a Trench Isolation with Rounded Corners

IP.com Disclosure Number: IPCOM000012081D
Original Publication Date: 2003-Apr-07
Included in the Prior Art Database: 2003-Apr-07
Document File: 2 page(s) / 206K

Publishing Venue

Motorola

Related People

R. Singh: AUTHOR [+5]

Abstract

For a system-on-a-chip solution, both logic and non-volatile memory devices have to be fabricated on the same chip. Though both circuits require large device densities, their isolation requirements differ. Non-volatile memory (NVM) devices require trenches with rounded corners while logic devices need the narrowest possible isolation with less corner rounding. The NVM bitcell requires rounded trench corners to avoid electrical field enhancement at trench corners during program and erase. These enhanced fields at non-rounded trench corners could reduce bitcell endurance and reliability. One technique to produce rounded trench corners is to grow a thick trench liner oxide at high temperature. However, thick liner results in excessive active width loss and poor fill of narrow trenches. The latter results in trench voids. As long as the spacing between the active regions is large enough, as it is in NVM arrays, trench liner thickness does not degrade the trench fill process. However, with increasing circuit densities in logic circuits, as the active spaces become smaller, it becomes harder to fill the narrow trenches with thick trench liners used in embedded NVM circuits.

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Fabricating a Trench Isolation with Rounded Corners

 

R. Singh, X. Bai *, R. Mora, P. Ingersoll and L. Parker

Motorola Inc., Ed Bluestein Boulevard, Austin, TX, 78751

* Micron Technology, Boise, ID

Problem

For a system-on-a-chip solution, both logic and non-volatile memory devices have to be fabricated on the same chip. Though both circuits require large device densities, their isolation requirements differ. Non-volatile memory (NVM) devices require trenches with rounded corners while logic devices need the narrowest possible isolation with less corner rounding. The NVM bitcell requires rounded trench corners to avoid electrical field enhancement at trench corners during program and erase.  These enhanced fields at non-rounded trench corners could reduce bitcell endurance and reliability.  One technique to produce rounded trench corners is to grow a thick trench liner oxide at high temperature. However, thick liner results in excessive active width loss and poor fill of narrow trenches.  The latter results in trench voids.  As long as the spacing between the active regions is large enough, as it is in NVM arrays, trench liner thickness does not degrade the trench fill process.  However, with increasing circuit densities in logic circuits, as the active spaces become smaller, it becomes harder to fill the narrow trenches with thick trench liners used in embedded NVM circuits.

Solution

The fabrication method disclosed here describes a shallow trench isolation (STI) integration to achieve the desired amount of trench corner rounding in the embedded NVM arrays without compromising the ability to fill narrow trenches in the logic regions with the...