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Timing Margin Improvement with Dual Vref and Receiver for Source Synchronous or Common Clock Single-Ended Bus

IP.com Disclosure Number: IPCOM000012122D
Publication Date: 2003-Apr-09
Document File: 3 page(s) / 80K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method that uses dual reference voltages (Vrefs) to improve the timing margin for a source synchronous or common clock single-ended bus.

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Timing Margin Improvement with Dual Vref and Receiver for Source Synchronous or Common Clock Single-Ended Bus

Disclosed is a method that uses dual reference voltages (Vrefs) to improve the timing margin for a source synchronous or common clock single-ended bus.

Background

The performance of a high-speed, single-ended bus is limited by signal integrity (such as simultaneous switching noise, inter-symbol interference, ledge or ringing on transitions, slower edge rate at the receiver, etc.). This signal integrity limits or impedes the performance of dual processor FSB at around 667MT/s. Usually, the faster edge of a signal increases the timing margins at the receiving agents. However, the faster edge rate severely degrades signal integrity in a multi-drop bus or an impedance-mismatched topology. Slower edge rate produces better signal quality at transitions, but it generally increases the susceptibility of a timing margin to Vref and power supply noise.

Current source synchronous buses use one receiver with one Vref; this solution makes it more difficult to meet higher performance due to source synchronous (SS) timings.

General Description

The disclosed method adopts dual receivers for the data path, with dual Vrefs to improve the timing margin. Two different Vref levels are used for two receivers separately. One receiver has a larger setup/hold time window for one electrical state (high or low state), and the other receiver has a larger setup/hold time window for the other electrical state. A mux selection controlled by the electrical state of the previous strobe or clock cycles determines which receiver path is the right path for the in...