Dismiss
InnovationQ will be updated on Sunday, Oct. 22, from 10am ET - noon. You may experience brief service interruptions during that time.
Browse Prior Art Database

Method for hiding chipset PCI devices in a low-cost implementation

IP.com Disclosure Number: IPCOM000012124D
Publication Date: 2003-Apr-09
Document File: 2 page(s) / 47K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for hiding chipset PCI devices in a low-cost implementation. Benefits include improved functionality, improved performance, and improved cost effectiveness.

This text was extracted from a Microsoft Word document.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 54% of the total text.

Method for hiding chipset PCI devices in a low-cost implementation

Disclosed is a method for hiding chipset PCI devices in a low-cost implementation. Benefits include improved functionality, improved performance, and improved cost effectiveness.

Background

        � � � � � Peripheral Component Interface (PCI) Local Bus Specification version 2.3 (PCI v2.3) was released March 20, 2002 by the PCI-SIG organization. With this standard, the PCI class code and header type registers are read only.

        � � � � � PCI Express (an I/O environment) Spec. 1.0 rel. date 7/23/2002 defines a packetized protocol and a load/store architecture.        � � � � �

        � � � � � Chipsets are conventionally implemented as multiple PCI devices within a single piece of silicon. This approach enables standard software to enumerate and configure devices so that it does not care about the physical implementation. Following this precedence, input/output (I/O) interfaces (such as PCI, PCI Express, and other high-speed parallel chip-to-chip mezzanine-level interfaces) are frequently implemented as PCI-to-PCI (P2P) bridges (see Figure 1).

        � � � � � Conventionally, chipset label elements are controlled by BIOS only as a host bridge class. In Figure 1, the chipset elements include the memory controller and front-side bus (FSB) registers. PCI Express interfaces are each represented with a PCI-to-PCI bridge to maintain legacy PCI software compatibility. When an OS determines that a device is host bridge class, it is ignored.

        � � � � � Two examples indicate why an internal device might be hidden:

•        � � � � During one generation, an internal device is controlled exclusively by hardware and BIOS. Later, the model evolves to one where a driver is written specifically for that device. Issues, such as operating system (OS) resource reallocation and hotplug, occur when the older-generation device is used. The newer model is more general-purpose but requires resources to own and write the driver.

•        � � � � A device must function below a chipset P2P bridge...