Browse Prior Art Database

Method for minimizing MTRR consumption using memory type precedence

IP.com Disclosure Number: IPCOM000012191D
Publication Date: 2003-Apr-16
Document File: 6 page(s) / 47K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for minimizing memory type range register (MTRR) consumption using memory type precedence. Benefits include improved performance and improved design flexibility.

This text was extracted from a Microsoft Word document.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 28% of the total text.

Method for minimizing MTRR consumption using memory type precedence

Disclosed is a method for minimizing memory type range register (MTRR) consumption using memory type precedence.� Benefits include improved performance and improved design flexibility.

Background

        � � � � � Thirty-two-bit processors implement model-specific registers called MTRRs. They provide the capability for software to associate ranges of system address space with various processor cache attributes including:

•        � � � � Write-back (WB)

•        � � � � Write-through (WT)

•        � � � � Write-combining (WC)

•        � � � � Write-protected (WP)

•        � � � � Uncacheable (UC)

        � � � � � A set of variable range MTRRs enables software to specify the memory type for eight variable-size address ranges. Each address range is defined by a MTRR pair containing the physical address base (with memory type) and the physical address mask. The MTRR pair imposes restrictions on the address range size and alignment. Most importantly, the range size must be a power of 2 and its base address must be aligned on the same power-of-2 boundary.

        � � � � � If two or more MTRR address ranges overlap with different memory types, memory type precedence is determined by the following rules:

1.        � � If one type is UC, the UC type is used.

2.        � � If the types are WT and WB, the WT type is used.
3.        � � Other combinations are undefined.

        � � � � � As memory size increases and the system address map grows in complexity, the maximum number of variable range MTRRs becomes a significant limitation. When the maximum size of memory increases relative to minimum granularity, additional MTRR pairs are required to describe extra address bits. Conventional MTRR allocation algorithms can require more than eight MTRR pairs to fully describe the system address map on existing chipsets.� Operating systems can also require the system BIOS to reserve MTRR pairs for runtime use.

        � � � � � For example, some memory controllers limit the maximum amount of physical memory to 16 GB minus 64 MB (MCH register DRB7 = 0xFF). In this case, the conventional MTRR allocation algorithm breaks down when adding ranges (base, size) to describe WB cacheable memory:

WB = (0, 8 GB) + (8 GB, 4 GB) + (12 GB, 2 GB) + (14 GB, 1 GB) + (15 GB, 512 MB) + (15.5 GB, 256 MB) + (15.75 GB, 128 MB) + (15.875 GB, 64 MB). This allocation consumes eight MTRR pairs and fails to describe the UC PCI range below 4 GB.

        � � � � � In this situation, the typical system BIOS would either hang or fail to describe the full amount of cached memory. During system boot, the BIOS might report less memory to the operating system or allow a portion of memory to use the default MTRR type.

        � � � � � Instead, the system BIOS can utilize memory type precedence rules to reduce MTRR consumption. Rather than adding up ranges of the same memory type, BIOS can overlay ranges of different memory types.

General description

        � � � � � The disclosed method minimizes MTRR consumption using memory type pr...