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Dual Supply Pass-Gate Configuration

IP.com Disclosure Number: IPCOM000012429D
Original Publication Date: 2003-May-07
Included in the Prior Art Database: 2003-May-07
Document File: 3 page(s) / 78K

Publishing Venue

IBM

Abstract

A means will be illustrated wherein a separate power connection is employed for control based inversion on pass-gate circuits that eliminate the need for levels translators when said pass-gate circuits are connected to a low power supply, Vddl, and any of the data inputs are driven from circuits connected to a higher power supply, Vddh. This approach will reduce the number of levels translators needed in a voltage island based design and lower the overall power while improving performance.

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Dual Supply Pass-Gate Configuration

  Power dissipation is becoming very critical in the design of VLSI systems. Numerous techniques are being employed to reduce both active and standby power. On such approach is to utilize the concept of voltage islands wherein two or more voltages are integrated on the same chip where the lower voltages are applied to the less power critical circuits. In order to have the circuits on the various voltage terrains communicate with one another it is often necessary to employ circuits termed, levels translators. These circuits are used whenever a circuit on a lower voltage supply needs to communicate with circuits on a higher supply. Figure 1 illustrates this approach. Levels translation is generally required only when a circuit on a lower voltage supply (Vddl) interfaces with one on a higher voltage supply (Vddh). This arises due to the leakage current that will result as the pfet device in a CMOS configuration circuit connected to the higher voltage supply due to the voltage difference between Vddl and Vddh. This approach is very well understood. For the best power efficiency, it is desirable to minimize the number of levels translators needed as each translator itself dissipates both power, occupies area and adds to the overall delay.

Vddl

Figure 1 : Basic Illustration of Levels Translation for Circuits Operating on two distinct supplies

    A problem often arises when a pass-gate circuit configuration having an integrated control inverter is to be connected to the low voltage supply and any of it's data inputs are driven by a high voltage circuit. This configuration disobeys the general rule that a high voltage circuit can drive a low voltage circuit directly without the need of a levels translator. Hence, what is needed is a means to allow a pass-gate circuit configuration with integrated control inverter(s) to be driven by circuits connected to a high voltage supply when said pass-gate circuits are connected to a low power supply.

    Figure 2 illustrates a simple 2:1 multiplexor having an integrated inverter to support the inverted control generation. The multiplexor is to be powered by the low voltage supply and hence, so is the integrated control inverter. Now if either of this circuit's data inputs are being driven by a circuit on the high voltage supply a leakage path can exist.

1

Vddl Vddh

Vddh

Vddl

Ckts

  Levels Translator

Vddh

Ckts

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V1

Gnd

D0

D1

P N

P N

V1

INT

Figure 2: Simple 2:1 Pass-gate style multiplexor

    This can be seen when a logical "0", 0 volts, is applied to the D0 input and a logical "1", Vddh is applied to the D1 input, while the SE signal is "0". In this case...