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Method for asymmetric bumps for controlled collapse chip connect

IP.com Disclosure Number: IPCOM000012430D
Publication Date: 2003-May-07
Document File: 2 page(s) / 36K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for asymmetric bumps for controlled collapse chip connect (C4). Benefits include improved functionality and improved performance.

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Method for asymmetric bumps for controlled collapse chip connect

Disclosed is a method for asymmetric bumps for controlled collapse chip connect (C4). Benefits include improved functionality and improved performance.

Background

� � � � � The silicon die of CPUs and chipsets is electrically coupled to the package using arrays of uniformly sized solder bumps in a process called C4 (see Figure 1). The red and green circles represent Vcc and Vss bumps, respectively.

        � � � � � Solder bumps can only handle a limited amount of current without being destroyed. The current limit for a bump is highly dependent on the direction current travels through the bump.

� � � � � Because the supply current density has been increasing for an extended time, the bump current limit presently poses a significant barrier to future performance improvements. This situation appears to be one of the largest technical gaps facing future processors.

Description

� � � � � The disclosed method is asymmetric bumps for the C4 process. Two different bump sizes are used with a single part. The smaller bump carries current in the less destructive direction. The larger bump carries current in the more destructive direction (see Figure 2). In this example, the Vcc bumps have been enlarged and the Vss bumps have been shrunk so that relative bump-to-bump spacing is preserved while enabling significantly higher current density.

Advantages

        � � � � � The disclosed method provides advantages, including:

•        � � � � Impro...