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Method for a spacer-less stack-die package design by dual-side wire bonding

IP.com Disclosure Number: IPCOM000012431D
Publication Date: 2003-May-07
Document File: 3 page(s) / 80K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for a spacerless stack-die package design using dual-side wire bonding. Benefits include improved functionality, improved support for future technologies, and improved cost effectiveness.

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Method for a spacer-less stack-die package design by dual-side wire bonding

Disclosed is a method for a spacerless stack-die package design using dual-side wire bonding.� Benefits include improved functionality, improved support for future technologies, and improved cost effectiveness.

Background

        � � � � � The trend of packaging is to combine several silicon (Si) devices into one package so that motherboard space can be saved, and the cost of package assembly can potentially be reduced.

        � � � � � Conventionally, one die is attached to silicon using a ball grid array (BGA) package (see Figure 1). Stacking a second die on the top of the first die has been problematic. The second die must be smaller than the first one to accommodate the bond pads requirement on the first die. A Si spacer may be inserted between the two dice to accommodate the requirements for wire bonding if the bottom die is equal or smaller than the top die (see Figure 2).

General description

        � � � � � The disclosed method is a package design to house stack dice without a spacer. The two thin dice are bonded to each other with a die attachment between them. The top die is wire bonded as a conventional BGA package. The bottom die is down bonded through the sunroof openings of the package substrate. The disclosed method is compatible with the conventional BGA package external dimensions.

        � � � � � The key element of the method includes:

•        � � � � BGA substrate with sunroof openings and two thin dice

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