Browse Prior Art Database

Method for a discrete flipped stacked package configuration

IP.com Disclosure Number: IPCOM000012434D
Publication Date: 2003-May-07
Document File: 3 page(s) / 58K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for a discrete flipped stacked package configuration. Benefits include improved yield.

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Method for a discrete flipped stacked package configuration

Disclosed is a method for a discrete flipped stacked package configuration. Benefits include improved yield.

Background

        � � � � � Logic die can have very poor yields. Adding a logic die to a stacked package creates the situation where the poor logic yield can cause a good package to be scrapped because the rest of the stack is bad. This issue is compounded when more than one logic die is added to the stack.

        � � � � � Conventional stacked package requires periphery ball grid array for the top package stack. This solution requires two different substrate designs and packages for the same functionality.

        � � � � � Standard packaging technologies include:

•        � � � � Folded chip scale package (see Figure 1)

•        � � � � Stacked Package Concept (see Figure 2)

•        � � � � Stack chip scale package (see Figure 3)

General description

        � � � � � The disclosed method is package stacking, utilizing a flipped package-stacking configuration for multiple logic-die stacking. The key elements of the method include:

•        � � � � Taking two (or more) separate discrete packages that have been electrically tested to determine known good die and flipping one package on top of the other

•        � � � � Interconnecting the two packages together using a wire bond package interconnect method or an interposer with solder balls

Advantages

        � � � � � The disclosed method provides advantages, including:

•        � � � � Improved yield due to eliminating compound yield loss because only known good die are included in a stack

•        � � � � Improved cost effectiveness due to eliminating the requirement for a new substrate design and package for the same functional unit to work in the conventional stacked package configuration

Detailed description

        � � � � � The disclosed method is package stacking. Two separate logic packages can be stacked in a flipped configuration to reduce z-height and enable known good-die testing. The method eliminates compound yield loss. An additional top package st...