Browse Prior Art Database

Memory mirroring for same bus attached SDRAM and DDR SDRAM

IP.com Disclosure Number: IPCOM000012445D
Original Publication Date: 2003-May-07
Included in the Prior Art Database: 2003-May-07
Document File: 2 page(s) / 41K

Publishing Venue

IBM

Abstract

A method to support memory mirroring on a bus containing multiple independent SDRAM or DDR SDRAM DIMMs.

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Memory mirroring for same bus attached SDRAM and DDR SDRAM

       This invention describes a method to support memory mirroring on a bus containing multiple independent SDRAM or

DDR SDRAM DIMMs. In standard computer systems, the memory controller can correct single bit errors and detect multibit errors. Certain chipset also have the ability to correct some multibit errors. This invention would provide the chipset the ability to correct all multibit errors allowing the system to continue to run and thus reducing unscheduled downtime.

     This invention operates by mirroring the data contained in one DIMM on a secondary DIMM of the same organization. The two DIMMs must be on the same memory data and address bus. In the course of sending a command to the DIMM, the chipset would drive the chip selects of the primary and secondary DIMM simultaneously. This will cause the command and subsequently any data transmitted on the bus to be stored in both the primary and secondary DIMMs. By applying the same command to both DIMM's the system can be assured that the DIMMs are in the same state. The only difference occurs when a read data transfer is to take place. Upon issuing a read command, only the primary DIMM's chip select will be selected. This will ensure that I/O contention will not occur since only one DIMM will be driving data. If the chipset detects an uncorrectable memory error during a read from the primary DIMM, it can perform the same read transaction to the secondary DIMM...