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Data transfer method in Processor Local Bus

IP.com Disclosure Number: IPCOM000012568D
Original Publication Date: 2003-May-15
Included in the Prior Art Database: 2003-May-15
Document File: 3 page(s) / 66K

Publishing Venue

IBM

Abstract

The method described here uses a split bus technique to improve data throughput. In the split bus, address bus, read data, and write data can be transferred independently. When read data or write data bus is used a bus master, other master must wait until the bus becomes empty. But if another bus is empty, by changing transfer type from read to write or write to read, two read cycles or write cycles operate at the same time.

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Data transfer method in Processor Local Bus

   IBM provides the CoreConnect bus for SoC (System on Chip). The feature of this bus is to separate address, read data, and write data bus and can operate each bus independently. Because of this, both read cycle and write cycle perform at the same period. Fig 1 shows this feature. Both write and read cycles are initiated at the same time.

Clock

Read Write

Write

Master A Master B

Read

Xf Ac Xfer AAck Xfer AAck Xfer AAck

Xfer DAck Xfer DAck Xfer DAck Xfer DAck

Xfer DAck Xfer DAck Xfer DAck Xfer DAck

Req Xfer AAck Req Xfer AAck

Req Xfer AAck

Re Xf Ac

Address

Write Data Read Data

Fig 1

Fig 2 shows the typical block diagram of a SoC. In this diagram boot code and application program is stored in ROM (Flash ROM) and main memory is used for a display frame buffer to reduce cost. Data for LCD is stored in the main memory and this data must be transferred to LCD controller within some period. If data can~ft be transferred to LCD controller within this period, a distortion or flicker will be observed on a LCD display. As LCD size becomes bigger and bigger, this traffic between the memory controller and the LCD controller becomes heavier. As PLB provides a good throughput and the LCD controller has FIFO to store some data in it, no problem with normal operation. But if PLB is occupied with a very low speed device during a long period this issue will occur. To reduce a cost, a Flash ROM is used to store boot code and an application program. A Flash ROM is a slow device and if cache miss is occurred, a processor initiates an instruction fetch cycle to fill a cache line. To fill a cache line, a long burst cycle must be used and during this cycle the LCD controller can~ ft get PLB and send data to LCD. To avoid this situation, a bus bridge is used to separate bus. A memory controller and LCD controller are placed on the secondary PLB. When the primary PLB is busy because of a cache line fill, the secondary PLB is empty and LCD controller can get data from main memory. But this method has several demerits: First is the main memory is placed on the secondary PLB and this degrades the system performance. The second is the complexity of a bus bridge module. This needs more gates and more die area. This increases chip cost.

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OPB

Processor

DMA UART Controller

Timer

PLB

GPIO

External Bus Controller

Memory Controller...