Browse Prior Art Database

Network SRAM Architecture

IP.com Disclosure Number: IPCOM000012573D
Original Publication Date: 2003-May-15
Included in the Prior Art Database: 2003-May-15
Document File: 2 page(s) / 24K

Publishing Venue

IBM

Abstract

Disclosed is an SRAM architecture for an industry-standard QDR-SRAM product. The concept improves access and cycle time by approximately 15% compared to conventional architectures. The new architecture also simplifies the data bus structure, including multiplexing and data wiring.

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Network SRAM Architecture

  Figure 1 below shows the concept. The Sextant architecture accommodates both x18 and x36 pin assignments. Unlike conventional architectures, the sextant architecture is divided into non-binarily addressable segments called sextants (S0-S5). Each sextant provides a small section of the I/O width. From the figure below, each sextant provides three bits of data for Byte A and three bits of data for Byte B. One subarray in each sextant is selected to provide all 36 bits of data. The Byte mapping is integrated into the subarrray; each subarray provides three A-bits and 3 B-bits (or C and D bits on sextants S0-S2) .In a x18 configuration, the three A-bits and 3-B-bits within a subarrray are locally multiplexed

into the 3-A bits bus. The access path of the data bus is shown in red and blue for Byte A and Byte B, respectively. Each sextant has a localized data bus that services a section of the I/O. This greatly reduces the data-line delay.

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Disclosed by International Business Machines Corporation

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