Browse Prior Art Database

Dispatch, Issue, Completion Throttling in SMT

IP.com Disclosure Number: IPCOM000012588D
Original Publication Date: 2003-May-16
Included in the Prior Art Database: 2003-May-16
Document File: 2 page(s) / 40K

Publishing Venue

IBM

Abstract

In an SMT processor core it is desirable to be able to throttle instruction flow, on a per-thread basis, at multiple points in the pipeline. Disclosed is a method for throttling instructions at Dispatch, Issue, and Completion.

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Dispatch, Issue, Completion Throttling in SMT

A group that is attempting to dispatch, can be rejected for various reasons, including debug workarounds. When rejected, an instruction group simply tries to dispatch again, until all conditions for rejecting have been cleared. At Instruction Dispatch, the disclosed throttling mechanism includes the following properties: - control to avoid back to back dispatches. - control to require N rejected dispatches every M successful dispatches, N and M controllable via programmable counters. - windowing of throttling enablement, so that throttling occurs only during specified debug time windows. - selection of various debug events, by thread, to start and end the throttling window. - ability to take a "debug" marked instruction group and require N dispatch rejects of that group before it can be dispatched. - ability to recognize a "debug" marked instruction group and require N dispatch rejects of a subsequent group before it can be dispatched. - ability to allow dispatch then disallow dispatch for certain cycle counts if a dispatch group is present, instead of counting actual dispatches and dispatch rejects.

At issue time, instructions on selected threads can be blocked from issuing. An issue throttling mechanism is disclosed with the following properties: - blocking issue for X cycles and allowing issue for Y cycles, where X and Y are programmable.
- ability to have throttling always enabled. - ability to have throttling trig...