Dismiss
InnovationQ will be updated on Sunday, Oct. 22, from 10am ET - noon. You may experience brief service interruptions during that time.
Browse Prior Art Database

SMT btag wrap dispatch reject

IP.com Disclosure Number: IPCOM000012589D
Original Publication Date: 2003-May-16
Included in the Prior Art Database: 2003-May-16
Document File: 3 page(s) / 63K

Publishing Venue

IBM

Abstract

Disclosed is a method for avoiding branch instruction queue overrun in an SMT processor core utilizing a split branch instruction queue and shared decode pipeline.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 52% of the total text.

Page 1 of 3

SMT btag wrap dispatch reject

In a high performance SMT processor core, a branch instruction queue (BIQ) may be utilized by the Instruction Fetch Unit (IFU) to track branch instructions, which may or may not yet have been dispatched, issued, or executed. A branch's position in the queue is referred to as the BTAG, or branch tag. When a fetched branch is sent down the decode pipe, it carries with it it's assigned btag.

If the BIQ is full for a thread, the assigned btag will wrap around to a position already in use. It is possible for this branch to reach the Dispatch stage before it has been written into the BIQ. A mechanism is required to keep this wrapping btag from being dispatched, since if the IFU were to see a branch dispatched and issued with a wrapped btag, logic failure in the IFU could occur, due to aliasing with an older branch occupying the same BIQ position.

Disclosed is a method for SMT BTAG wrap detection at dispatch, which keeps a wrapped btag from being dispatched, whether the processor core is operating in a single threaded or multi-threaded mode. Note that in multi-threaded mode, the BIQ is divided equally between the threads, but the decode pipeline is shared.

Shown in the Instruction Fetch Unit (IFU) / Instruction Decode Unit (IDU) section of the Figure is a BIQ, in SMT configuration, with two write pointers (1 per thread). Also shown is a block representing the fetch/decode pipeline, which sources instructions to the Instruction Sequencing Unit (ISU). The instruction group sourced to the ISU contains the branch tag (BTAG) for the group. This BTAG corresponds to the branch's position in the BIQ. BTAGs remain active in the BIQ until the branch completes, and in a BIQ full condition, the oldest branch position in the BIQ will be the position next written into.

When the instruction group is dispatched by the ISU, an entry is made in the Global Completion Table (GCT), and that entry includes the BTAG. Each thread owns a "tail pointer", which is the address into the GCT of the oldest instruction group for...