Browse Prior Art Database

SMT address trickling

IP.com Disclosure Number: IPCOM000012658D
Original Publication Date: 2003-May-19
Included in the Prior Art Database: 2003-May-19
Document File: 6 page(s) / 114K

Publishing Venue

IBM

Abstract

In an SMT processor core with a shared instruction decode/dispatch pipeline, a means is required for a thread with an exception to obtain its next instruction address (NIA), even if the pipeline is blocked by another thread. Disclosed is a method for obtaining that address, utilizing Dispatch Flushes and cache line buffer (CLB) holds. Also disclosed is an alternate mode of operation to allow for more conservative handling of this function, without the dispatch flush requirement. Further, a dispatch fairness mode is disclosed to ensure forward progress is made by any thread, in the presence of dispatch flushes for exception handling.

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SMT address trickling

When taking a synchronous or asynchronous exception, it is often necessary to save the next instruction address (NIA) in a save-restore register (SRR0) such that the OS can eventually return to the NIA after handling the exception. The refetch to the exception handler is done by the Completion unit, which cannot always compute the NIA from the current instruction address (CIA) due to branch targets that are not known by the Completion unit. The NIA is obtained through an "address trickle-down" process, wherein prior to the current SMT design, the address bus portion of the front-end pipeline would stabilize on the NIA after a known amount of time and could be captured by the Completion unit.

In an SMT processor design, the stabilization of the NIA on the front-end pipeline can no longer be relied upon as before, since the front-end pipe must handle addresses for multiple threads of execution. Providing separate address bus pipelines for each thread would be prohibitive in terms of area, wiring, and power. The disclosed method for SMT NIA address trickling for exception handling consists of: - address trickling by one thread at a time only - new interface signal "address_ok_for_trickle" to validate the address bus, even when the instruction group is not valid - an address trickle dispatch flush, used by a thread to get another thread cleared out of the front-end pipe, so that the desired thread's address can proceed down the pipe - an address trickle CLB hold, used by a thread to hold of decode of the other thread to ensure that decode cycles are given to the thread that is waiting on a trickle address - use of an address thread bit, in conjunction with address_ok_for_trickle, to make sure correct thread's NIA is captured.

Shown in Figure 1 is an Instruction Fetch Unit (IFU), feeding reloaded cache lines to thread specific cache line buffers (CLBs). The Instruction Decode Unit (IDU) selects which thread's CLB to decode instructions from for forwarding down to Dispatch. Dispatched instruction groups are loaded into the Completion Table, and logic associated with the Completion Table can assert "CLB hold" signals to tell the IDU to only choose from one particular CLB. (This is to insure that the thread that needs its NIA will eventually see it, regardless of thread decode priority). Also shown is the path for the dispatch address to be loaded into the NIA register, which can subsequently be put into the architected Save-Restore register (SRR0).

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If a thread needs its NIA during exception handling, and the shared front-end pipeline is blocked by the other thread, the thread with the exception will perform a Dispatch Flush of the blocking thread. This removes the blocking thread's instruction groups from the entire front-end pipeline so that the thread with the exception will have the opportunity to obtain its NIA. With the CLB hold asserted for the previously blocking thread, it is guaranteed the exc...