Browse Prior Art Database

SMT Issue Serialization

IP.com Disclosure Number: IPCOM000012663D
Original Publication Date: 2003-May-19
Included in the Prior Art Database: 2003-May-19
Document File: 2 page(s) / 41K

Publishing Venue

IBM

Abstract

In SMT, there is a need to force instruction from either thread to be completion serialized issue (i.e next-to-complete instruction issue) for debug and failure workarounds. This mechanism has to be performed by each thread at the issue queue.

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SMT Issue Serialization

The embodiment of the disclosure is shown in Figure 1. The issue queue will have a thread bit per entry to indicate which thread a particular queue entry belongs to. Also, each instruction in the issue queue will have an instruction ID, and a "serialize" bit. When the "serialize" bit is active, the instruction will have to wait until it is the oldest instruction in the processor before it can be issued to the execution unit (i.e next-to-complete issue).

At dispatch time, the dispatcher can force the "serialize" bit to 1 on any instruction of a particular thread for a number of reasons (debug, workarounds etc...). When the "serialize" bit is active for an instruction in the issue queue, that instruction will have to monitor the completion ID to see if it is the oldest instruction of that thread in the processor. This can be done by comparing the instruction ID with the completion ID, along with the thread bits. If the compare is a match, then the instruction is the oldest instruction of that thread; for this case, the "serialize" bit will be turned off to indicate that the instruction is now available for issuing.

Figure1: Embodiment of disclosure

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Disclosed by International Business Machines Corporation

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