Engineered Wires design database
Original Publication Date: 2003-May-20
Included in the Prior Art Database: 2003-May-20
This disclosure describe a design methodology for managing enginnered wires on a System on a Chip (SOC) designs. Due to the large distances that signals need to travel, wire delay is becoming more and more critital to meeting frequency targets. Therefore these wires need to be design and carefully specified. This is a tedious and error prone work and it needs a methodoly such as this invention to manage the design.
Engineered Wires design database
System On Chip (SOC) design have large amount of interconnect wires. Usually the buffering and repowering of these wires are not entered in a High Level Design Description language such as VHDL or Verilog. Usually these are post processed in the netlist by the chip integrator. However as these SOC design gets larger, these interconnect wires are now becoming more timing critical. They need to get from one point of the chip to another in a set timing requirement or else the design may loose performance and cycle time. To achieve these requirements these interconnect wires are now designed: ie their wire characteristic, path, buffering and repowering are specified by the designer in order to guarantee that the signal arrives at the required time. These "Engineered Wires" are not post processed in the netlist by the chip integrator because there is no guarantee that they will have the required wire characteristic and properties. Therefore, the buffering and repowing of these wires are described by the designed in the High Level Design Language (HDL) such as VHDL or Verilog.
The advantages of describing the "Engineered Wires" in an HDL are as follow:
Buses are grouped together and each bit will receive the same design parameters. No need to have a custom design for each bit in a bus Buffers and repowering blocks are unique or "custom" for each bus. This allows fine tuning of the drivers for the wires characteristics. Also these custom blocks will have precise pin outs that line up the routes with previous and next blocks. This will guarantee that wires have a straight shot with no turns or "jogs". These blocks have a placeable position in the chip floorplan; therefore guarantee stability in the design characteristics. This in contrast with netlist post processing which the buffers are usually "generic type" and their placement is dependent of what other nets are close by. There is no guarantee on the design characteristics.
However, describing the "Engineered Wires" in HDL has some problems:
It is very tedious and error prone to describe each bus. An HDL is a very type intensive language which requires a lot of typing to describe a function. With large design and with many busses the HDL description file is usually very large. This problem gets complicated when "slit buffers" are used in the design. Slit buffers are custom buffers design to fit in a narrow space. Buses and wires that need to be tapped in these buffers need a HDL port description, circuit specification on the HDL of the slit buffer. When these slit buffers gets large, this is a very tedious work. This problem is compounded as many "slit buffers" are used in the chip. HDL languages does not provide ways to annotate wire characteristics, such as wire width, wire metal layer, wire spacing, wire shielding, wire neighborhs, wire cross talk and hostility. This work is done manually which is very error prone. A bigger problem is maintaining th...