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Method For A Single Clock Architecture For Gigabit Ethernet

IP.com Disclosure Number: IPCOM000012720D
Publication Date: 2003-May-21
Document File: 4 page(s) / 126K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for a single clock architecture for Gigabit Ethernet. Benefits include improved functionality, improved power performance, and improved support for future technology.

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Method For A Single Clock Architecture For Gigabit Ethernet

Disclosed is a method for a single clock architecture for Gigabit Ethernet. Benefits include improved functionality, improved power performance, and improved support for future technology.

Background

      In conventional gigabit Ethernet, the PHY signal is defined so that after auto-negotiating, the two sides resolve which device is master and which is slave. The master does not adjust its transmit clock. The slave uses its recovered clock of one channel as its transmit clock.

      The Gigabit Ethernet standard (IEEE 802.3ab,) enables a clock difference between the two sides of +/-100 ppm. The slave must continuously adjust its transmit clock phase and frequency to the recovered clock. This procedure typically requires the use of a timing loop or phase interpolator for adjusting the transmitter’s clock phase and frequency.

      In the proposed architecture, the slave-mode clock has a frequency of 5 times the symbol rate, such as 625 MHz vs. 125 MHz, but a different over-sampling ratio may be used.

General description

      The disclosed method is single clock architecture for a Gigabit Ethernet network device. The method enables a precise, well-balanced clock with low jitter, low area, and low power for receiving and transmitting data. The method eliminates the requirement for multiple timing devices, such as:

•             Delay lock loop (DLL)

•             Synchronous delay line (SDL)

•             Phase lock loop (PLL)

•             Phase interpolator

      As a result, the circuitry is reduced in area, cost, and power. The analog clock design is considerably simplified.

Advantages

              The disclosed method provides advantages, including:

•             Improved functionality due to providing single clock architecture for gigabit Ethernet technology 

•             Improved power performance due to eliminating the requirement for multiple timing devices

•             Improved support for future technology due to improving the circuitry size by eliminating the requirement for multiple timing devices

•             Improved cost effectiveness due to eliminating the requirement for multiple timing devices

•             Improved cost effectiveness due to simplifying the analog clock design

Detailed description

      The single clock architecture addresses the challenge of having a transmitter with a continuously changing clock. In slave mode, the requirement to adjust the phase and frequency according to the recovered channel A is eliminated.

      The transmitter is comprised of a transmit digital/analog converter (TDAC), which operates with the same clock as the receiver. In slave mode, the data driving the TDAC is continuously...