Browse Prior Art Database

Hardware Cycle Based Memory Residency

IP.com Disclosure Number: IPCOM000012728D
Original Publication Date: 2003-May-22
Included in the Prior Art Database: 2003-May-22
Document File: 2 page(s) / 40K

Publishing Venue

IBM

Abstract

Hardware Cycle Based Memory Residency implementation over traditional time based, or software based method addresses cache rehit probabilities and the overhead of scanning and freeing memory, and having pages stay resident in memory for long periods of time. This invention may be better for performance by relying on the hardware cycle counter rather than the system clock or software methods for freeing memory pages.

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Hardware Cycle Based Memory Residency

The problem solved by this invention is the overhead of scanning memory and having pages stay resident in memory for long periods of times. One solution addresses this by releasing pages after they are read in or written out by the application, but this takes away the cache rehits, if they should occur. Another solution addresses memory-resident pages by running a daemon at a given interval, but this daemon, syncd, scans all of memory, and if there are a large number of pages to be written out to disk, it can cause considerable slowdown, in addition the period of time between scans may be too long if the cache rehit rate takes place in a relatively small amount of time. The current method, LRU, does a two pass scan. On the first pass, if the page has been recently referenced, it will reset the reference bit, and then move to the next page. If the next page is free it will give it to the requesting process. If there are no pages, it will do a second pass through memory.

This invention addresses the limitations of previous solutions by introducing a new method of freeing pages from memory while allowing for the probability of cache hits.

When a page is requested, the page frame table for that page will be updated with the counter value for the hardware cycle counter. When LRU runs, if the value in the PFT cycle counter is a value greater than a timeout value from the current hardware cycle counter, then that page is immediately released and made available for the application, at which time the PFT cycle counter gets updated for that page.

With the use of the hardware cycle counter, we avoid the expensive cost of checking the system clock and making a time comparison based on that me...