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Simultaneous Multithreading (SMT) Independent Status Bit Usage

IP.com Disclosure Number: IPCOM000012755D
Original Publication Date: 2003-May-27
Included in the Prior Art Database: 2003-May-27
Document File: 2 page(s) / 41K

Publishing Venue

IBM

Abstract

In SMT mode, the register renaming logic must support the status of the physical registers for each thread simultaneously. The status bits that indicate which physical registers are being used by either thread are contained in single vector. When one thread is allocating new registers, the other thread could be freeing up registers via a flush or completion operation

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Simultaneous Multithreading (SMT) Independent Status Bit Usage

The mapper has shadow registers to restore the mapper table to a correct state after a flush. The shadow registers is updated every time new instruction is dispatched. In single thread mode, the shadow registers is an array of 1 write/1 read. In SMT mode, a second read port is required to restore the status of each thread independently after a flush. At any time, when a flush for one thread is initiated, its old status (older than the flush point) can be read out of the shadow registers and restored to the mapper table. In SMT, both threads can initiate a flush simultaneously, hence, 2 read ports are required to read out old status of both threads to restore to the mapper.

A thread bit is also required in the mapper to indicate which thread a register is mapped to. One thread bit is required for each of the register entry in the mapper. When one thread is allocating an entry at dispatch time, the thread bit in that location is also updated to reflect that this thread is now using this entry. When an instruction is dispatched, its source registers will access the mapper to determine its dependency on the previous instruction's target register. The thread bit of the dispatching instruction will be compared with the thread bit in the mapper at the accessed location. If the registers matched, and the thread bits are also matched, then there is a direct dependency between the dispatching instruction and an...