Browse Prior Art Database

Method for a universal dual-mode high-voltage PMOS decoupling capacitor

IP.com Disclosure Number: IPCOM000012789D
Publication Date: 2003-May-28
Document File: 9 page(s) / 358K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for a universal dual-mode high-voltage positive-channel metal oxide semiconductor (PMOS) decoupling capacitor. Benefits include improved functionality, improved performance, improved power performance, important ease of implementation, and improved support for legacy applications.

This text was extracted from a Microsoft Word document.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 28% of the total text.

Method for a universal dual-mode high-voltage PMOS decoupling capacitor

Disclosed is a method for a universal dual-mode high-voltage positive-channel metal oxide semiconductor (PMOS) decoupling capacitor. Benefits include improved functionality, improved performance, improved power performance, important ease of implementation, and improved support for legacy applications.

Background

        � � � � � On-die decoupling structures are intended to provide a low-impedance path for power supply noise. They reduce the variation in the relative voltage between the power supply rails.

        � � � � � Conventional solutions include the following:

•        � � � � Inversion mode capacitor used for low voltage power-rail decoupling

•        � � � � High-voltage decoupling capacitor

•        � � � � Reverse-biased PN junction diode

•        � � � � MIM capacitor

        � � � � � A conventional inversion mode capacitor offers high capacitance per unit area (see Figure 1). However, the capacitor is not suited for high voltage applications where the gate-source/gate-drain voltage exceeds the limit set for reliable operation for a given process. An inversion mode capacitor stack uses the Ibias current to hold the floating nodes at a known level. The value n depends on the voltage to be decoupled. For a 1.5V tolerant process, n=3 for safely decoupling 3.3V.

        � � � � � A high-voltage decoupling capacitor is constructed using a stack of inversion mode capacitors (see Figure 2). This configuration overcomes the limitations of the inversion mode capacitor. However, the high-voltage decoupling capacitor has poor capacitance per unit area because of the series capacitor configuration and the added area penalty of accommodating more than one transistor. Also required for this configuration is a weak-bias circuit that consumes current to prevent the intermediate nodes of the capacitor from floating to dangerously high/low voltage levels.

        � � � � � A high-voltage decoupling capacitor constructed using a reverse-biased PN junction diode suffers from a very low capacitance per unit area because of charge depletion in the junction region (see Figure 3).

        � � � � � A high voltage decoupling capacitor constructed as a MIM structure suffers from a very low capacitance per unit area because of relatively thick dielectric between the metal layers (see Figure 4). To support MIM capacitors, extra processing steps are generally required.

        � � � � � None of these conventional solutions simultaneously provides decoupling for both high and low voltage power supplies using one unified structure without two discrete capacitors for each power rail.

        � � � � � The following terms are used inter-changeably throughout the disclosure.

•        � � � � Ground ↔ GND ↔ VSS ↔ 0.0V

•        � � � � VCC ↔ Low Voltage Power Supply ↔ Core Power ↔ 1.5V

•        � � � � VCCP ↔ High Voltage Power Supply ↔ I/O Power ↔ 3.3V

General description

        � � � � � The disclosed method provides on-die decoupling for high voltage power rails using a spec...