Browse Prior Art Database

Method for a pseudo-TSOP

IP.com Disclosure Number: IPCOM000012799D
Publication Date: 2003-May-28
Document File: 5 page(s) / 95K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for a pseudo-thin small-outline package (pseudo-TSOP). Benefits include improved performance and improved ease of implementation.

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Method for a pseudo-TSOP

Disclosed is a method for a pseudo-thin small-outline package (pseudo-TSOP). Benefits include improved performance and improved ease of implementation.

Background

        � � � � � Some customers prefer TSOP packaging with one Vssq pin and one Vccq pin (see Figures 1 and 2). Extra pairs of Vccq and Vssq bonds have been added on the die to achieve faster device performance, but they cannot all be connected to a single lead on a TSOP (see Figure 3). For example, a typical flash die has three pairs of Vccq and Vssq pads on the die but only one pair is powered on the standard 56 lead TSOP. All three pairs are powered on a very fine ball grid array (VFBGA) package. The die assembled in a TSOP is inherently 6 ns slower because of the missing Vccq and Vssq connections.

General description

        � � � � � The disclosed method is a pseudo-TSOP. It looks like a TSOP from the outside, but inside the package, a 2-layer metal substrate is used to route the signals identically to the vfBGA package. All the power supplies on a die can be powered and connected to the lead finger on the package. The speed of the product is 6 ns faster than when in a standard TSOP. When the die is placed in smaller pin count packages, the extra power supplies are not included and the die’s performance is slightly slower.

Advantages

        � � � � � The disclosed method provides advantages, including:

•        � � � � Improved performance due to enabling a TSOP to meet faster speed specifications

•        � � � � Improved ease of implementation due to enabling the use of older assembly equipment

Detailed description

        � � � � � The disclosed method can be implemented in three ways. Option 1 adds a substrate and inserts an extra process step to the conventional TSOP assembly process. The die is bonded to the substrate before the substrate is bonded to the lead finger (an added wire bond step). The substrate is a two-sided printed circuit board (PCB, see Figure 4). This configuration provides the advantage of enabling all die power supplies to be connected to the lead finger. For example, four Vccq pads exist on the die, but the package has only one Vccq finger. Because the die has four pads, four wires connect Vccq from the die. They are shorted together on the substrate. A single...