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Design and Process for Solder Joint Compensation and Optimization for Flip-Chip Assemblies

IP.com Disclosure Number: IPCOM000012807D
Original Publication Date: 2003-May-28
Included in the Prior Art Database: 2003-May-28
Document File: 5 page(s) / 295K

Publishing Venue

Motorola

Related People

Betty Yeung: AUTHOR [+7]

Abstract

The joining of organic substrates and silicon dice that have very different coefficients of thermal expansion (CTE) generates stress on the solder joint during assembly cooling from the solder solidification temperature. The stress in the joints is a function of the distance of the joint from the neutral point (DNP). In the flip-chip assembly, the neutral point is at the center of the die. Therefore, the outermost bumps are subject to highest stress. For some bump systems, the stress concentrations at given locations will be high enough to cause either delamination to the interface or cracking the device underneath. The preferred condition is that the solder will deform under the stress while the integrity of the interfaces is maintained. Typically, with same pad size for both device and substrate, the reflowed solder bumps will have a symmetrical geometry and the stress concentration point is at the interface between solder and UBM. Changing the shape of the joints can have the effect of decreasing the stress occurring at the interface and forcing deformation in the solder. This addresses the problems of premature solder cracking, UBM cracking, intermetallic cracking, delamination, while also meeting the needs of continual trends in technologies where pitches are increasingly fine, reflow temperatures are increasingly large, and dies have greater functionality and size. The modified solder joints are achieved through reduction of solder volume, shifting the pad locations, and change in the ratio of pad sizes between the device and substrate - this is done for the outer bumps. The inner bumps, left unchanged, are utilized to provide standoff for the modified bumps. A stress decrease of almost 50% is realized in the modified solder configuration as compared to the typical solder joint shape.

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Design and Process for Solder Joint Compensation and Optimization for Flip-Chip Assemblies

Betty Yeung, Harold Downey, Yifan Guo, Shun-Meen Kuo, Bill Stone, Charles Zhang, Jeff Zhao

Abstract

The joining of organic substrates and silicon dice that have very different coefficients of thermal expansion (CTE) generates stress on the solder joint during assembly cooling from the solder solidification temperature. The stress in the joints is a function of the distance of the joint from the neutral point (DNP). In the flip-chip assembly, the neutral point is at the center of the die. Therefore, the outermost bumps are subject to highest stress. For some bump systems, the stress concentrations at given locations will be high enough to cause either delamination to the interface or cracking the device underneath. The preferred condition is that the solder will deform under the stress while the integrity of the interfaces is maintained. Typically, with same pad size for both device and substrate, the reflowed solder bumps will have a symmetrical geometry and the stress concentration point is at the interface between solder and UBM. Changing the shape of the joints can have the effect of decreasing the stress occurring at the interface and forcing deformation in the solder. This addresses the problems of premature solder cracking, UBM cracking, intermetallic cracking, delamination, while also meeting the needs of continual trends in technologies where pitches are increasingly fine, reflow temperatures are increasingly large, and dies have greater functionality and size. The modified solder joints are achieved through reduction of solder volume, shifting the pad locations, and change in the ratio of pad sizes between the device and substrate - this is done for the outer bumps. The inner bumps, left unchanged, are utilized to provide standoff for the modified bumps. A stress decrease of almost 50% is realized in the modified solder configuration as compared to the typical solder joint shape.

Introduction

In flip-chip packages, during the die attach process, the silicon device and organic substrate are joined with solder bumps. Organic substrates and silicon die have very different coefficients of thermal expansion (CTE), 20ppm/°C vs. 2.6ppm/°C. When the die and the substrate are joined, this difference in the thermal expansion causes stress in the solder joint. The thermal stress in the joints is a function of the distance of the joint from the neutral point (DNP), the thermal excursion between the solder melting/solidification temperature and room temperature (dT), and the difference in CTE’s between the die and the substrate.  The greater the DNP, the higher the dT, and the higher the CTE mismatch, the greater the stress will be.  In the flip-chip assembly, where the neutral point is at the center of the die, the outermost bumps are subject to the highest stress.  Locally, these high stresses are concentrated at the corners of the bumps.

The stress c...