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Parallel Access to Embedded Test Access Ports (TAPs)

IP.com Disclosure Number: IPCOM000012810D
Original Publication Date: 2003-May-29
Included in the Prior Art Database: 2003-May-29
Document File: 3 page(s) / 43K

Publishing Venue

IBM

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Parallel Access to Embedded Test Access Ports (TAPs)

   Disclosed is a method for accessing test structures within intellectual property (IP) blocks embedded on a system-on-a-chip (SoC). Provided that each IP block has a standard Test Access Port (TAP), test structures within any such block can be accessed via a single chip-level TAP.

The chip-level TAP must be designed with an instruction register of length K+L, where

K ? ( length of longest instruction register among TAPs in embedded IP blocks ) and 2L ? N , where
N ? ( # of TAPs in embedded IP blocks )

The L low-order bits of the instruction register will be used for selecting access to the TAP within one of N IP blocks or for selecting a chip-level instruction (such as EXTEST, BYPASS, IDCODE, etc). When the TAP within one of the embedded IP blocks is accessed by the L low-order bits of the instruction register, up to K high-order bits of the instruction register are used for selecting an instruction within the selected IP block.

Any TAP provides ACCESS signals for enabling the Test Data Register (TDR) selected by the current instruction to be connected to the TAP pins for data register operations. Each such ACCESS signal is active (1) when (and only when) the TDR enabled by the ACCESS signal is to be selected by the current instruction. For the cases where the L

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low-order bits of the chip's instruction register contain the code for selecting a specific embedded IP block, the ACCESS signal corresponding to that instruction is used for enabling access to the TAP within the selected IP block, as if that TAP were the selected TDR.

The TAP within each embedded IP block is connected as follows:

The TDI input of the embedded TAP is sourced from the chip's TDI input. The TDO output of the embedded TAP is connected to the chip's TDO multiplexing logic, such that data from the embedded TAP is propagated to the chip's TDO pin when the ACCESS signal corresponding to the embedded IP block is active and the chip's TAP is in the Shift-DR state. The TCK input of the embedded TAP is sourced from the chip's TCK input. If the embedded TAP has a TRST...