Method and System for System on Chip Framework Verification
Publication Date: 2003-Jun-05
The IP.com Prior Art Database
A method and system for testing and verifying the framework of a system on chip design is provided. Behavioral models are associated with a device under test which is representative of an integrated circuit. The behavioral models are able to be utilized in a repeated fashion to test components of the device under test when implemented in combination to verify the operation of the device under test without having to rewrite behavioral constructs upon subsequent testing.
METHOD AND SYSTEM FOR
SYSTEM ON CHIP FRAMEWORK VERIFICATION
METHOD AND SYSTEM FOR SYSTEM ON CHIP FRAMEWORK VERIFICATION
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to the field of systems on-chip, and specifically to a method and apparatus for a system on chip verification framework.
2. Background Information
Hardware description languages (HDLs) such as Verilog and VHDL provide a textual format for describing electronic circuits and systems and can be used for verification through simulation, for timing analysis, for test analysis and for logic synthesis. Verilog is codified in IEEE Standard No. 1364.
HDLs such as Verilog have both structural constructs and behavioral constructs. In the structural side of Verilog a design can be specified at the gate or at the register transfer level. This structural description can then be converted by a process called synthesis to reduce the design to a specific set of gates for actual construction of the chip.
Behavioral constructs or models specify a design in terms of a sequence of functions, operations or instructions. The models, provided in Verilog or other HDL source code format, are tools for system designers to exercise and debug the design of components. The objective of the models is to aid in the functional verification process and to reduce timing errors prior to silicon fabrication.
At present, behavioral constructs are written on an ad hoc basis for each design element separately. Thus, each component of a system on chip (SoC), such as intellectual property (IP) cores, busses, and interfaces, has its own test environment, set
of behavioral models and test suites. Verification of components that are integrated into a SoC requires rewriting of behavioral constructs and test suites so that they can be used together. This is time consuming and costly.
BRIEF DESCRIPTION OF THE DRAWINGS 5 Figure 1 illustrates a block diagram of a system on chip verification framework, according to an example of the present invention.
Figure 2 illustrates a block diagram of a template for a behavioral model, according to an example of the present invention.
In the following detailed description of the preferred embodiments, reference is made to the accompanying drawings which form a part hereof and in which is shown by way of illustration of specific embodiments. These embodiments are described in sufficient detail to enable persons skilled in the art to practice the invention, and it is to be understood that other embodiments may be utilized and that logical, mechanical and electrical changes may be made without departing from the scope of the present invention. The following detailed description is, therefore, not to be taken in a limiting sense. The present invention concerns a system and method for using the same behavioral constructs again and again, so that components of a syste...