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New Package Design for Stacked Flip Chips

IP.com Disclosure Number: IPCOM000012930D
Publication Date: 2003-Jun-11
Document File: 3 page(s) / 272K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method that introduces a new package design to house stacked flip chip dice without a spacer. Benefits include a reduction in the overall package height, as well as costs associated with packaging.

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New Package Design for Stacked Flip Chips

Disclosed is a method that introduces a new package design to house stacked flip chip dice without a spacer. Benefits include a reduction in the overall package height, as well as costs associated with packaging.

Background

The trend in packaging is to combine several Si devices into one package, so that motherboard space is saved and the cost of the package assembly is reduced. The current state of art is to stack one die on the top of the other die; each die is connected to the package substrate by bonding wires (see Figures 1 and 2).

General Description

The disclosed method is shown in Figure 3. The dice are attached using a die attach material. The top die is a flash memory, while the bottom side is a logic device. Each die is individually connected to the package substrate by C4 die bumps. A high-thermal conductive epoxy is used as an underfill material between the die and the package substrate. This epoxy is also used as a die-attach material between the dice. A metal heat spreader is also attached on the top of the package to help dissipate the heat to the external ambient. If necessary, an additional heat sink can be attached to the top of the metal heat spreader to reduce thermal resistance.

Figure 4 shows another embodiment of the disclosed method. In this case, the entire package cavity is completely filled with the high-thermal conductive epoxy between the dice, and between the die and the package substrate. The flip chip...