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Method for adaptive loadline control circuitry for a multiple processor computer system

IP.com Disclosure Number: IPCOM000012939D
Publication Date: 2003-Jun-11
Document File: 4 page(s) / 48K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for adaptive loadline control circuitry for a multiple processor computer system. Benefits include improved functionality, improved performance, and improved reliability.

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Method for adaptive loadline control circuitry for a multiple processor computer system

Disclosed is a method for adaptive loadline control circuitry for a multiple processor computer system. Benefits include improved functionality, improved performance, and improved reliability.

Background

� � � � � In a multiple processor (MP) or dual processor (DP) computer system, the power supply must provide enough current capacity to meet the power demands of the multiple processors at their peak load. The system loadline is often designed to be to quite shallow (low impedance) to meet the minimum operating voltage requirement for the processors. An added complexity is that in practice all sockets are not necessarily always populated. The conventional design solution is to enable the voltage regulator module (VRM) to sense the presence of each processor and decrease the loadline if more sockets are occupied. For example, the loadline for a fully populated DP system is lower than that for a half-populated system. A problem arises, however, with this approach. For example, in a DP system, both processors can be plugged in and sensed by the VRM, but the load is not evenly distributed between them. One unit may draw much more current than the other.

� � � � � The worst case is when one processor is at maximum load while the other is idle. Because the VRM does not detect the actual load of the two processors, the loadline is kept unnecessarily low. This problem is clearly unique to a multiprocessor system and has a significant impact on system reliability. When loadline and total load are both low, the voltage on the processors is unnecessarily high, shortening their life, particularly for the one with the higher load. However, if one of the processor fails, the system fails.

        � � � � � For a multiple processor system, reliability is compromised by the requirement to meet the performance target. When all processors are plugged in, the system loadline is reduced to a very low value to meet the performance target, compromising reliability. The processor with the most load (highest Icc) fails first, bringing the whole system down.

        � � � � � No ideal solution exists conventionally. The typical solution is to prioritize performance over reliability by designing a shallow loadline to meet the worst-case condition for performance.

� � � � � To illustrate the concept, the block schematic of a DP system loadline configuration includes two processors, two VRMs, and a shared common power plane (see Figure 1). The worst-case use condition for performance is when both sockets are populated and all processors have the maximum load. In this case, the two resistors, Rvr, can be viewed as two resistors in parallel, and the system loadline is reduced. A shallow loadline is designed to meet the Vccmin requirement. However, in reality, all processors are rarely at maximum load simultaneously. As a result, voltage on a high-load unit is kept unnecessarily high, compromising syst...