Browse Prior Art Database

Autonomic Parallel Small Computer Systems Interface SCSI error recovery

IP.com Disclosure Number: IPCOM000012955D
Original Publication Date: 2003-Jun-11
Included in the Prior Art Database: 2003-Jun-11
Document File: 1 page(s) / 38K

Publishing Venue

IBM

Abstract

The current parallel SCSI architecture does not contain error handling protocols for handling multiple identical SCSI id's on one bus. This type of configuration will typically halt all communication on the bus until the problem is resolved by the system operator. This article proposes an error recovery strategy that will remove duplicate SCSI id's from the bus and allow normal communication to continue.

This text was extracted from a PDF file.
This is the abbreviated version, containing approximately 100% of the total text.

Page 1 of 1

Autonomic Parallel Small Computer Systems Interface SCSI error recovery

Error recovery strategy:

1. In the event of five bus reset events in five minutes (or some other time span that will identify serious bus communication problems) all devices shall start bus arbitration with all target ids set. Devices that are programmed with this error recovery strategy shall not select during this arbitration cycle.

    a. If any device on the bus selects during the arbitration cycle, it will be understood that the device does not comply with the error recovery strategy. At this point error recovery will stop due to non-compliant devices being present on the bus.

2. After one bus free phase equivalent to two selection timeout phases (this shall be known as an error time phase) the device at id 0 will arbitrate for itself. The beginning of this phase shall be known as time zero.

    a. If there is a corresponding selection, it will be assumed that there is an id conflict present on the bus. All devices that participated in the arbitration/selection shall cease all SCSI bus communication until the next power cycle.

3. All remaining ids shall start self arbitration after the following time delay:

time zero + bus id * error time phase

Disclosed by International Business Machines Corporation

1