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Delta-Sigma Modulator with Better Linear Characteristics Multilevel (RZ) Return to Zero Analog to Digital converter

IP.com Disclosure Number: IPCOM000012982D
Original Publication Date: 2002-Jul-01
Included in the Prior Art Database: 2003-Jun-11
Document File: 1 page(s) / 44K

Publishing Venue

IBM

Abstract

Continuous-Time Delta-Sigma Modulator is a solution for high-speed, high-resolution A/D (Analog to Digital) converters. Excess loop delay [1] (delay between the quantizer clock edge and the time when a change in output bit us seen at the feedback point in the modulator) degrades the performance of Delta-Sigma modulator since it’s unpredictable and the right parameters can’t be determined before manufacturing. The way to make the circuit unaffected by the unknown excess loop delay is to use RZ (Return to Zero DAC (Digital to Analog Converter) [1]. The implementation of 2-levels DAC is quite simple to implement with differential logic. The implementation of multilevel DAC, which can help the implementation of modulator with lower sampling rate and lower OSR (Over Sampling Ratio), is harder task. In this invention I try to give a solution for RZ multilevel DAC. In other invention I presented a way to implement a Delta-Sigma Modulator with RZ multilevel DAC, assuming that we have RZ 2-level DAC. A block diagram of the preceding architecture is followed: The output of the A/D is the input to a LUT (Look-Up-Table). According to the A/D output (every sampling period) the LUT will divide the RZ DACs into 3 sets: Set #1 all the RZ DACs that will output negative RZ pulse. Set #2 all the RZ DACs that will output positive RZ pulse. Set #3 all the RZ DACs that will output zero pulse (this set is optional). The LUT will choose those 3 sets (or 2 sets) such that the output of the header will give the desired RZ multilevel pulse. A very important parameter is the linearity and accuracy of the RZ DAC.

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  Delta-Sigma Modulator with Better Linear Characteristics Multilevel (RZ) Return to Zero Analog to Digital converter

Continuous-Time Delta-Sigma Modulator is a solution for high-speed, high-resolution A/D (Analog to Digital) converters. Excess loop delay [1] (delay between the quantizer clock edge and the time when a change in output bit us seen at the feedback point in the modulator) degrades the performance of Delta-Sigma modulator since it's unpredictable and the right parameters can't be determined before manufacturing. The way to make the circuit unaffected by the unknown excess loop delay is to use RZ (Return to Zero DAC (Digital to Analog Converter) [1]. The implementation of 2-levels DAC is quite simple to implement with differential logic. The implementation of multilevel DAC, which can help the implementation of modulator with lower sampling rate and lower OSR (Over Sampling Ratio), is harder task.

     In this invention I try to give a solution for RZ multilevel DAC. In other invention I presented a way to implement a Delta-Sigma Modulator with RZ multilevel DAC, assuming that we have RZ 2-level DAC. A block diagram of the preceding architecture is followed:

     The output of the A/D is the input to a LUT (Look-Up-Table). According to the A/D output (every sampling period) the LUT will divide the RZ DACs into 3 sets: Set #1 - all the RZ DACs that will output negative RZ pulse. Set #2 - all the RZ DACs that will output positive RZ pulse. Set #3 - all the RZ DACs...