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Method for pipeline throttling for power management

IP.com Disclosure Number: IPCOM000012992D
Publication Date: 2003-Jun-12
Document File: 3 page(s) / 87K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for pipeline throttling for power management. Benefits include improved thermal performance, improved reliability, and improved power performance.

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Method for pipeline throttling for power management

Disclosed is a method for pipeline throttling for power management. Benefits include improved thermal performance, improved reliability, and improved power performance.

Background

              The amount of heat that is generated by a device is dependent on the power consumption of various subsystems on the chip. However, the heat must be controlled or the chip can burn out.

              Conventional solutions focus on limiting (throttling) memory to reduce power consumption.

General description

      The disclosed method is a power management mechanism to reduce the power consumption of the graphics-rendering pipeline by throttling its throughput. As a result, the temperature of the hardware is reduced and a catastrophic event is prevented.

      The disclosed method limits the processing engine, such as the graphic rendering pipeline, to reduce the overall power consumption of the system. The processing engine typically consumes most of the die area in an integrated graphic product. If the processing engine is the dominant heat source on the die, the disclosed method is the effective way to reduce the power to lower the die temperature.

Advantages

              The disclosed method provides advantages, including:

•             Improved thermal performance due to limiting heat production and preventing the part from damaging itself

•             Improved reliability due to preventing a thermal virus

•             Improved power performance due to saving power and enhancing battery life in mobile chipsets

Detailed description

      The disclosed method is comprised of two portions:

•             Throttle duty-cycle controller

•             Operation controller

Throttle duty-cycle controller

      The throttle duty cycle specifies the number of clocks within a 16-clock period in which data may be passed between the memory interface (local cache) and the rendering pipeline. The throttling value is specified from 0 to 15. This value can be converted to the percentage of the duty cycle being throttled, which is computed as (value * 100/16)%. Th...