Browse Prior Art Database

METHOD FOR IMPLEMENTING PRECISE EXCEPTIONS

IP.com Disclosure Number: IPCOM000013024D
Original Publication Date: 2000-Mar-01
Included in the Prior Art Database: 2003-Jun-12
Document File: 4 page(s) / 63K

Publishing Venue

IBM

Abstract

Precise exceptions are an important part of the specification in many architectures. (This is true for both real architectures and virtual machines such as the Java Virtual Machine) The present invention describes how to achieve correct implementation of such architectures during binary translation when speculation and instruction scheduling are to be used to achieve high perform- ance.

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METHOD FOR IMPLEMENTING PRECISE EXCEPTIONS

Precise exceptions are an important part of the specification in many architectures. (This is true for both real architectures and virtual machines such as the Java Virtual Machine) The present invention describes how to achieve correct implementation of such architectures during binary translation when speculation and instruction scheduling are to be used to achieve high perform- ance.

The present invention describes a code generation technique and runtime environment to be used for implementing precise exceptions while preserving scheduling freedom. The present invention has multiple applications, such as in the binary trans- lation of CISC architectures or in scheduling of unsafe oper- ations.

BINARY TRANSLATION OF CISC ARCHITECTURES ________________________________________

When using system-level binary translation in CISC architectures, correct exception and trap points must be recognized at the CISC instruction boundary even when a CISC instruction has been cracked into multiple execution primitives. When using an incre- mental commit strategy, atomic instruction execution can be achieved by establishing whether an instruction will succeed before actually modifying any architected processor state.

An example is the translation of the load multiple instruction LM. Consider the translation LM RG=(0,7), 0x10(8) into RISC-like execution primitives:

LWZ R0, 0x10(R8)

LWZ R1, 0x14(R8)

LWZ R2, 0x18(R8)

LWZ R3, 0x1C(R8)

LWZ R4, 0x20(R8) (*)

LWZ R5, 0x14(R8)

LWZ R6, 0x18(R8)

LWZ R7, 0x1C(R8)

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When the memory area referenced by the load sequence spans a page boundary (e.g., at address 0x20(R8) as indicated by the asterisk), and the second page is not program accessible, taking an exception at that point would violate the atomicity require- ment, since the instruction cannot be completed successfully, but part of the architected processor state has already been obliter- ated by the partial execution of the LM primitives. This is usually resolved by probing the high end of the addressable data range using a victim "probe" instruction, e.g.:

LWZ RTMP, 0x1C(R8) (+)

LWZ R0, 0x10(R8)

LWZ R1, 0x14(R8)

LWZ R2, 0x18(R8)

LWZ R3, 0x1C(R8)

LWZ R4, 0x20(R8) (*)

LWZ R5, 0x14(R8)

LWZ R6, 0x18(R8)

LWZ R7, 0x1C(R8)

In the case where an LM sequence spans a page boundary at the location indicated by the asterisk, an exception would be raised by the first victim load instruction into an unarchitected resource marked by +. (For the store multiple SM instruction, a special probe-store instruction needs to be provided which tests for write permissions but does not actually change the target location.)

While pre-probing can be used to establish atomic behavior for exceptions due to easy to predict and test conditions such as page boundary crossings, it is not sufficient to establish atomic exceptions in the presence of hardware support for a PER-mechanism (which allows to establish data breakpoints on th...