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Method And Apparatus For Reliable Clock Domain Transfer

IP.com Disclosure Number: IPCOM000013143D
Publication Date: 2003-Jun-16
Document File: 3 page(s) / 334K

Publishing Venue

The IP.com Prior Art Database

Abstract

A method and apparatus for reliably effectuating a transfer of data, clocked in a first clock domain, using a first clock signal, to a second clock domain where a second clock signal is used. A skip signal indicates whether to ignore a clock transition edge of the clock signal in the second clock domain, according to the relative positions of clock edge transitions of the first and second clock domains. In an embodiment, a phase locked loop (PLL) is used to generate a receive clock (rclk) that is employed by a chip interface to sample data using the receive clock signal, whichclk may be generated such that it is aligned and transitions at four times the frequency with respect to a master clock signal (MCLK) using the PLL. MCLK and rclk are in the first clock domain. In a specific embodiment, the PLL is employed to lock down the receive clock signal rclk to the incoming master clock signal MCLK using a feedback path in the PLL. Series connected Flip/flops are employed to generate a two bit gray coded cycle count signal. As rclk is divided down and aligned in a predetermined phase relationship with MCLK, an n-bit digital code, e.g., a 10 bit digital code, may be used to indicate the position or phase of rclk within a given cycle of MCLK. A comparison between the gray coded cycle count signal and a clock signal (PCLK) from the second clock domain (PCLK) indicates whether to skip a clock transition of PCLK when data is transferred between the clock domains of MCLK/rclk and PCLK.

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Method and Apparatus for Reliable Clock Domain Transfer

A method and apparatus for reliably effectuating a transfer of data between two different clock domains. This method and apparatus involves the generation of a skip signal to reliably transfer data clocked in a first clock domain, using a first clock signal to a second clock domain where a second clock signal is used. The skip signal indicates whether to ignore a clock transition edge of the clock signal in the second clock domain, according to the relative positions of clock edge transitions of the first and second clock domains.

    In an embodiment, a phase locked loop ("PLL") is used to generate a receive clock (rclk) that is employed by a chip interface to sample data using the receive clock signal rclk. As is illustrated in FIGURE 1, rclk may be generated such that it is aligned and transitions at four times the frequency with respect to a master clock signal (MCLK) using the PLL. MCLK and rclk are in the first clock domain.

FIGURE 1.

FIGURE 2. FIGURE 3.

     In a specific embodiment partially illustrated in FIGURE 2, the PLL is employed to lock down the receive clock signal rclk to the incoming master clock signal MCLK using a feedback path in the PLL. Series connected Flip/flops are employed to generate a two bit gray coded cycle count signal CycCnt <1:0> (i.e., representing cycle count bit signals CC<0> and CC<1>) from rclk and MCLK. FIGURE 3 illustrates the timing waveforms associated with the generation of the gray coded cycle count signal in the circuit shown in FIGURE 2.

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    As rclk is divided down and aligned in a predetermined phase re...