Browse Prior Art Database

Method for preserving DOS compatibility using remote IO subsystems.

IP.com Disclosure Number: IPCOM000013195D
Original Publication Date: 2001-Dec-25
Included in the Prior Art Database: 2003-Jun-17
Document File: 3 page(s) / 85K

Publishing Venue

IBM

Abstract

This invention solves the problem of preserving full DOS compatibility when designing large enterprise-class servers utilizing based processors. This invention achieves full DOS compatibility using a minimum number of signals to communicate between the CPU portion of the computer and the remote IO subsystem. This invention is applicable to implementations where the CPU complex and IO complex are physically separated by distances exceeding 15 meters. The main advantage of this invention is that full DOS compatibility can be preserved using a minimum of signals between the two physically separated subsystems.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 57% of the total text.

Page 1 of 3

Method for preserving DOS compatibility using remote IO subsystems.

This invention solves the problem of preserving full DOS compatibility when designing large enterprise-class servers utilizing based processors. This invention achieves full DOS compatibility using a minimum number of signals to communicate between the CPU portion of the computer and the remote IO subsystem. This invention is applicable to implementations where the CPU complex and IO complex are physically separated by distances exceeding 15 meters. The main advantage of this invention is that full DOS compatibility can be preserved using a minimum of signals between the two physically separated subsystems.

This invention creates an interface between the CPU subsystem and the remote IO subsystem to accommodate the communications of DOS compatibility signals between the two subsystems. The following describes an example interface between the two subsystems. However, this invention does not limit itself to this implementation only.

The interface between the CPU subsystem and the IO subsystem is a combination of electrical signals, referred to as sideband signals. The sideband interface uses a 20 pin MDR cable. The cable will contain an assembly of 10 twisted pairs surrounded by a shield. The pairs can either be single-ended or differentially driven, depending on the cable length between the two subsystems. The cable will contain full duplex serialized sideband buses (one in each direction). The twisted pairs are assigned as follows:

1. CEC-IO Serial Data
2. CEC-IO Serial Clock
3. CEC-IO Serial Strobe
4. IO-CEC Serial Data
5. IO-CEC Serial Clock
6. IO-CEC Serial Strobe

.

A serial clock is transmitted with each serialized data signal to avoid the use of phase locked loops for clock recovery. The serial strobe signal is used to identify the start of a serial frame. This avoids the use of encoder/decoder schemes with special characters assigned for recognizing the start and end of serial frames. FPGA's are used to generate and disassemble the serial data streams. Should the need for new signa...