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Method and apparatus for the selective scoreboarding of computation results

IP.com Disclosure Number: IPCOM000013280D
Original Publication Date: 2001-Jan-12
Included in the Prior Art Database: 2003-Jun-18
Document File: 2 page(s) / 54K

Publishing Venue

IBM

Abstract

Statically scheduled machines based on long instruction word architectures offer many benefits, among them a high amount of available parallelism and simple control structure due to compiler based scheduling. As a result, we expect statically scheduled machines to achieve higher frequency with simpler design than would be possible with out-of-order superscalar processor designs.

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Method and apparatus for the selective scoreboarding of computation results

Statically scheduled machines based on long instruction word architectures offer many benefits, among them a high amount of available parallelism and simple control structure due to compiler based scheduling. As a result, we expect statically scheduled machines to achieve higher frequency with simpler design than would be possible with out-of-order superscalar processor designs.

Statically scheduled machines do have a disadvantage when dealing with dynamic events, such as cache hit or miss detection. Early VLIW machines were designed without caches, to achieve predictability in memory access. However, such designs suffer in memory performance. To achieve high performance, VLIW architectures must have adequate support for using caches. A simple VLIW design might use an architecture based on a stall-on-miss design, whereby the entire processor is stalled when a cache miss occurs. This design point is the most natural design option for the static nature of VLIW architectures.

However, stall-on-miss introduces stalls even when there is no immediate use for the result which is loaded. This may occur because a load instruction has been scheduled early enough to allow ample time for cache miss service, or for a speculatively issued load which will never be used because an alternative path is executed instead. An alternative implementation choice is stall-on-use whereby the processor only stalls if a results is unavailable when another instruction attempts to access it. Availability of resources for implementing stall-on-use policies are usually based on scoreboarding.

Most modern machines employ scoreboarding to achieve good performance. In dynamically scheduled architectures, the appropriate logic is at the core of instruction dispatch and thus a required part of the functionality. However, stall-on-use logic and scoreboarding are more expensive to implement in statically scheduled machines since the aim of such machines is to eliminate most of the control logic which...