Browse Prior Art Database

Instruction and Data Address Tracing Technique for POWERPC Machines

IP.com Disclosure Number: IPCOM000013287D
Original Publication Date: 1999-Oct-01
Included in the Prior Art Database: 2003-Jun-18
Document File: 2 page(s) / 33K

Publishing Venue

IBM

Related People

LR SMOLDERS: AUTHOR

Abstract

Disclosed here is a new technique using a combination of the POWERPC* trace and performance monitor features to efficiently produce instruction and data traces.

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This is the abbreviated version, containing approximately 52% of the total text.

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Instruction and Data Address Tracing Technique for POWERPC Machines

Disclosed here is a new technique using a combination of the POWERPC* trace
and performance monitor features to efficiently produce instruction and data
traces.

     Providing instruction and address traces is a very important part of
system tuning and future system design. There are many different methodologies
for providing this support, each of which having its benefits and problems.
Software instruction and data address tracing tools usually either instrument
the code to be traced or use the tracing facility of the machine to
single-step though the code and decode all the instructions at each step
looking for load or store instructions.

     When using the instrumentation technique, one has to first discover the
basic blocks of the code to be traced which is a non trivial and usually slow
operation especially on machines with dynamic branches like all the POWERPC
based machines. When using the tracing facility of the processor, tracing
becomes extremely slow because of the necessary instruction decoding after
each instruction. In both cases, the data address must be calculated from the
decoding of the instruction interrupted, further slowing down the trace.

     The technique disclosed here uses a combination of four POWERPC features
to efficiently produce instruction and data address traces :

     1. POWERPC processors can be programmed to generate a trace interrupt
after each instruction (single-step mode).

     2. The facility described in [*], allows the tracing code to easily
recognize load, store and branch instructions without decoding anything. This
facility provides bits in a register indicating such instructions.

     3. The performance monitor facility of the POWERPC family allows the
processors to count instructions while excluding the tracing code itself. This
is achieved by using the Process Marking (PM) bit to trigger the counting.
Since this bit is automatically reset by hardware on interruptions, the trace
interrupt handler which does the tracing can easily be excluded from the
counting.

     4. The POWERPC Performance Monitor facilities have a register called SDA
which contains the effective data address used by the...