Browse Prior Art Database

Glitch Filter Using Data Setup/Hold Time to Validate Clocking Edge

IP.com Disclosure Number: IPCOM000013306D
Original Publication Date: 1999-Nov-01
Included in the Prior Art Database: 2003-Jun-18
Document File: 3 page(s) / 43K

Publishing Venue

IBM

Related People

Thomas Despins: AUTHOR

Abstract

Main Idea

This text was extracted from a PDF file.
This is the abbreviated version, containing approximately 52% of the total text.

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Glitch Filter Using Data Setup/Hold Time to Validate Clocking Edge

Main Idea

*Title of disclosure (in English)

Glitch Filter Using Data Setup/Hold Time to Validate Clocking Edge

*Idea of disclosure

The SCSI SPI-3 standard allows data to be captured on both the rising and falling edges of the ACK line. Each time there is an ACK transition, a determination must be made on the validity of the ACK edge. Therefore, it is necessary to filter out the invalid ACK transitions induced by line glitches. The current glitch filter implementation is not able to effectively filter out all invalid transitions and cannot determine which edge is valid and invalid if the glitch occurs close in time to a valid transition.

This invention filters out glitches on the ACK line by measuring the setup and hold times of the data lines. Only after the setup and hold times have been met will the data be considered valid thereby effectively eliminating glitches and clocking data only on the correct edge.

The patent value of this invention is not limited to just SCSI interfaces. It can be applied to any interface that uses a clock edge to capture data and requires a minimum setup and hold time.

The SCSI SPI-3 standard defines the required setup and hold times that must be met by the receiver to ensure valid data. The total time for which the data lines must not change must equal the setup time plus the hold time before the data can be considered valid. The invention monitors the data lines and starts a timer that will measure the setup time every time one of the data lines changes. See Fig. 1 which is the circuit used to monitor the data lines for changes.

The length of the setup timer and hold timers will be determined by measuring the length of time the counter takes to time one system clock. Th...