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Low Loss, Deuterium-Diffused SiON Material for Planar Optical Waveguide Circuits (SiON:D)

IP.com Disclosure Number: IPCOM000013324D
Original Publication Date: 2001-Jun-01
Included in the Prior Art Database: 2003-Jun-18
Document File: 2 page(s) / 32K

Publishing Venue

IBM

Abstract

For integrated (optical) planar lightwave circuits (PLC’s) used in optical access and switch devices, two material classes are currently in use: (a) semiconductor compounds (such as InP) and, (b) glass-based such as SiliconOxide (Silica) . In the latter category mainly two subsections exist: (i) Ge-doped SiO2 (similar to glassfiber) and (ii) ‘N’-doped SiO2, (SiON or silicon-oxy-nitride). The latter subcategory (SiON) is mainly fabricated for planar lightwave circuits. The optical propagation of information through such PLC’s should be as low-loss as possible, in order to design complex optical routings and switch matrices for such PLC devices. Materials with low optical loss are of high relevance to PLC fabrication and to optical circuit designers. The conventional planar Ge:SiO2 PLC’s have the advantage of using a well established base technology, however two drawbacks exist in transferring such Ge:SiO2 based technology for future PLC’s. First, the Ge:SiO2 manufacturing techniques are not suited for integration into standard IC fabrications as known in the electronic industry, so have some difficulty in following similar scaling trends. Secondly, the low optical contrast and optical confinement essentially a low-index step into the core material- limits the radius of curvature to typically 10- mm, hence the PLC layout density is low, as is the real-estate usage of the wafer. This latter issue very much limits an up-scaling in complexity (adding functions) and an economic scaling is only possible via an increase in wafer size (4-6-8" diameter), without achieving a more economic usage of wafer area. In contrast to the conventional Ge:SiO2 technology stands the SiON technology for PLC’s allowinga1mm turning radius, corresponding to a 10-100x increase in circuit layout density. Thus, significantly more complex devices can be manufactured on a moderately sized 4" diameter wafer, avoiding the necessity to resort to larger wafer diameters. The SiON core material allows a <1 mm turning radius, originally at the expense of unacceptably high optical propagation losses in the 1550nm transmission band due to the N-H chemical bond, inherent in this material. This loss disadvantage is solved by high-temperature anneals of the SiON core material in an Nitrogen environment with the effectthat the N-H bonds are cracked and H is diffused out. The method proposed here is to lower the optical propagation losses in SiON PLC’s with an alternate technique, based on

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  Low Loss, Deuterium-Diffused SiON Material for Planar Optical Waveguide Circuits (SiON:D)

For integrated (optical) planar lightwave circuits (PLC's) used
in optical access and switch devices, two material classes are
currently in use: (a) semiconductor compounds (such as InP) and,
(b) glass-based such as SiliconOxide (Silica) . In the latter
category mainly two subsections exist: (i) Ge-doped SiO2 (similar
to glassfiber) and (ii) 'N'-doped SiO2, (SiON or
silicon-oxy-nitride). The latter subcategory (SiON) is mainly
fabricated for planar lightwave circuits. The optical propagation
of information through such PLC's should be as low-loss as
possible, in order to design complex optical routings and switch
matrices for such PLC devices. Materials with low optical loss
are of high relevance to PLC fabrication and to optical circuit
designers.

The conventional planar Ge:SiO2 PLC's have the advantage of using
a well established base technology, however two drawbacks exist
in transferring such Ge:SiO2 based technology for future PLC's.
First, the Ge:SiO2 manufacturing techniques are not suited for
integration into standard IC fabrications as known in the
electronic industry, so have some difficulty in following similar
scaling trends. Secondly, the low optical contrast and optical
confinement - essentially a low-index step into the core
material- limits the radius of curvature to typically 10- mm,
hence the PLC layout density is low, as is the real-estate usage
of the wafer. This latter issue very much limits an up-scaling in
complexity (adding functions) and an economic scaling is only
possible via an increase in wafer size (4-6-8"...