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Data address line test for write once memorys

IP.com Disclosure Number: IPCOM000013331D
Original Publication Date: 1999-Nov-01
Included in the Prior Art Database: 2003-Jun-18
Document File: 3 page(s) / 68K

Publishing Venue

IBM

Related People

Tim Crockett: AUTHOR

Abstract

This disclosure describes a memory test algorithm that tests the address and data lines of a PROM device that allows multiple runs of the test without replacing the ROM. With normal memory tests, values are written to a set of addresses multiple times. Each time the test is repeated the current value can be erased and a new value written. For PROM or EPROM type memories the cleared state of an address is with all its bits set to '1'. Writing to the address consists of changing set bits to '0'. Once a bit is set to '0' it cannot be set back to '1'. When a conventional memory test writes to a PROM it can only be performed once. Each additional test run requires that the PROM be replaced with a blank. One of the goals of the memory test is to detect faults that have a low probability of occurrence such as timing faults. To do this the test must be performed multiple times. Replacing the PROM each time the test is run is not only impractical but almost useless. By comparing the value to be written to the value pressent at the target address it is possible to make the test repeatable. The test algorithm reads a list of address value pairs from a constant table. The address value pairs are chosen to thourghly exersise the address data lines to the PROM. Like a normal memory test, the values are written to their addresses according to the table and then read back and compared. The difference is that before each value is written it is ANDed with the value that is already present at the target address. If any bits at the target address are erroneously set to zero the AND of the current and new value will not equal the new value. If the AND of the two values is equal to the new value then it is possible to write the new value to the target address. Since the same values are always written to the same addresses this test can be performed multiple times without having to replace the PROM. Should the wrong value be written to a test address the read back loop will detect it and report it as a test failure. If the current value at the target address prevents the table value from being properly written the test exits with an invalid test message. If an invalid test message is received then the PROM must be replaced with a blank. 1 START

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Data address line test for write once memorys

   This disclosure describes a memory test algorithm that tests the address and data lines of a PROM device that allows multiple runs of the test without replacing the ROM. With normal memory tests, values are written to a set of addresses multiple times. Each time the test is repeated the current value can be erased and a new value written. For PROM or EPROM type memories the cleared state of an address is with all its bits set to '1'. Writing to the address consists of changing set bits to '0'. Once a bit is set to '0' it cannot be set back to '1'. When a conventional memory test writes to a PROM it can only be performed once. Each additional test run requires that the PROM be replaced with a blank. One of the goals of the memory test is to detect faults that have a low probability of occurrence such as timing faults. To do this the test must be performed multiple times. Replacing the PROM each time the test is run is not only impractical but almost useless. By comparing the value to be written to the value pressent at the target address it is possible to make the test repeatable.

   The test algorithm reads a list of address value pairs from a constant table. The address value pairs are chosen to thourghly exersise the address data lines to the PROM. Like a normal memory test, the values are written to their addresses according to the table and then read back and compared. The difference is that before each value is writ...