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Implementing the Return From System Call Vectored instruction in the Power 4 Microprocessor

IP.com Disclosure Number: IPCOM000013354D
Original Publication Date: 2000-Jun-01
Included in the Prior Art Database: 2003-Jun-18
Document File: 2 page(s) / 52K

Publishing Venue

IBM

Abstract

Implementing the Return From System Call Vectored instruction in the Power 4 Microprocessor Disclosed is a mechanism for supporting the Return From System Call Vectored instruction in the Power 4 superscalar, superpipelined, out-of-order gigahertz processor core. This instruction provides many challenges to an out-of-order processor, and these challenges were aggravated by the high frequency target of the design. This mechanism uses many existing mechanisms within the Power 4 core instruction control circuitry to satisfy the architectural requirements of the 'rfscv' PowerPC/AS instruction. This instruction is unique within the PowerPC/AS architecture; it has aspects that are similar to interrupts, and it has other aspects that are similar to branches. This instruction uses the Link Register as the return address; the Link Register is typically used for subroutine calls. Interrupts, however, use the Save and Restore Register 0 (SRR0) for the same purpose. Likewise, this instruction uses the Count Register in place of SRR1 to restore the Machine State Register (MSR). But, this instruction also acts very much like an interrupt in that it redirects the fetch address and alters the MSR.

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Implementing the Return From System Call Vectored instruction in the Power 4

Microprocessor

Disclosed is a mechanism for supporting the Return From System Call Vectored instruction in the Power 4 superscalar, superpipelined, out-of-order gigahertz processor core. This instruction provides many challenges to an out-of-order processor, and these challenges were aggravated by the high frequency target of the design.

This mechanism uses many existing mechanisms within the Power 4 core instruction control circuitry to satisfy the architectural requirements of the 'rfscv' PowerPC/AS instruction. This instruction is unique within the PowerPC/AS architecture; it has aspects that are similar to interrupts, and it has other aspects that are similar to branches. This instruction uses the Link Register as the return address; the Link Register is typically used for subroutine calls. Interrupts, however, use the Save and Restore Register 0 (SRR0) for the same purpose. Likewise, this instruction uses the Count Register in place of SRR1 to restore the Machine State Register (MSR). But, this instruction also acts very much like an interrupt in that it redirects the fetch address and alters the MSR.

The implementation of this mechanism uses the microcode table in the Power 4 processor core. This microcode table translates a single PowerPC/AS instruction into a series of grouped internal operations (IOPs). This processor achieves its high frequency goals by only supporting a limited set of instruction primitives, called internal operations, and organizing these IOPs into instruction groups (or simply groups). Four non-branch IOPs with a single branch IOP comprise a group. These groups define the allowable precise interrupt boundaries as well as provide issue control boundaries.

Table 1: 'rfscv' microcode sequence Group IOP1 IOP2 IOP3 IOP4 Branch_IOP 1 rfscv_mfctr eGPR0 noop noop noop branch_noop 2 mtmsr eGPR0 noop noop noop branch_noop 3 mflr eGPR0 noop noop noop branch_noop 4 mtnia eGPR0 noop noop noop branch_noop

The microcode table translates the PowerPC/AS instruction 'rfsvc' into four IOP groups. The first instruction in the first group is named 'rfscv_mfctr'. This IOP serves two purposes. First, it indicates to the global completion table (GCT) that a 'rfscv' instruction is pending, and that it should prevent any asynchronous interrupt from occurring until the 'rfscv' has been fully executed and committed. In addition, this instruction is issued to the Condition Register logic engine, which supports Special Purpose Register (SPR) reads for...