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Clamping Diode Dumps ESD Charge into Auxiliary Cap Rather than Vcc

IP.com Disclosure Number: IPCOM000013364D
Original Publication Date: 2001-Jun-14
Included in the Prior Art Database: 2003-Jun-18
Document File: 2 page(s) / 53K

Publishing Venue

IBM

Abstract

This invention allows components with a small time constant to be used for ESD protection of sensitive signal lines, yet it eliminates the potential problem of the power supply lines being disrupted by ESD noise. It does this by using one or more "auxiliary" capacitors to absorb the positive going ESD spike conducted by the clamping diodes that would normally be connected to +Vcc. The grounded side of the clamping diodes are connected to frame ground. The "auxiliary capacitors" can be large enough to absorb the ESD charge without the voltage getting to be too large.

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Clamping Diode Dumps ESD Charge into Auxiliary Cap Rather than Vcc

This invention allows components with a small time constant to be used for ESD protection of sensitive signal lines, yet it eliminates the potential problem of the power supply lines being disrupted by ESD noise. It does this by using one or more "auxiliary" capacitors to absorb the positive going ESD spike conducted by the clamping diodes that would normally be connected to +Vcc. The grounded side of the clamping diodes are connected to frame ground. The "auxiliary capacitors" can be large enough to absorb the ESD charge without the voltage getting to be too large.

This design enables the ESD spike to be absorbed without logic ground or +Vcc being "moved around" by the ESD spike. A large resistor value is in parallel with the "auxiliary" capacitors to bleed the charge off of it in a period of time. The auxiliary caps are connected to frame ground.

See the circuit illustrated below. In this case, it is the "J" line that is particularly sensitive to timing. The clamping diode pairs are DP1, DP2, DP5, and DP7 and the "auxiliary caps" are C101 - C104.

In this application, the circuits driving the "N" and "E" signals are strong enough and the size of the "auxiliary caps" are large enough to sustain a DC bias on the "auxiliary" caps such that they do not present a significant capacitive load on the operation of the signal lines. (When the driver circuits drive the signal lines to zero volts, the clamp...