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Browse Prior Art Database

REVERSE NANO CMOS

IP.com Disclosure Number: IPCOM000013390D
Original Publication Date: 2001-Apr-01
Included in the Prior Art Database: 2003-Jun-18
Document File: 1 page(s) / 25K

Publishing Venue

IBM

Abstract

A method is proposed to fabricate nanoelectronics, e.g. self assemply, contact printing, SPM fabrication, molecular electronics, micromechanical storage, single-molecule amplifiers, tunneling molecular elecrophotonics etc.. on CMOS processed microelectronic circuits. Electronic circuits are made starting with the electronic elements, then the first level of fine wiring is added, then more processing steps are used to put on more layers of wiring and interconnects. The more layers, the thicker the wiring gets. Now for a molecular approach which would use the wiring of CMOS the idea for a nanoelectronic circuit is as follows: REVERSE CMOS: Here it is started with a wafer with the higher level wiring and one goes progressively backwards till the surface is planar with the finest level wiring on the surface (M1, M0). Although one may not consider this the best way to make today's chips, a use in 2020 may be worthwhile.

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REVERSE NANO CMOS

   A method is proposed to fabricate nanoelectronics, e.g. self
assemply, contact printing, SPM fabrication, molecular electronics,
micromechanical storage, single-molecule amplifiers, tunneling
molecular elecrophotonics etc.. on CMOS processed microelectronic
circuits.

Electronic circuits are made starting with the electronic
elements, then the first level of fine wiring is added, then more
processing steps are used to put on more layers of wiring and
interconnects. The more layers, the thicker the wiring gets.

Now for a molecular approach which would use the wiring of CMOS
the idea for a nanoelectronic circuit is as follows:

REVERSE CMOS: Here it is started with a wafer with the higher
level wiring and one goes progressively backwards till the
surface is planar with the finest level wiring on the surface
(M1, M0). Although one may not consider this the best way to make
today's chips, a use in 2020 may be worthwhile.

The low-level wiring on the top would then be used to either use
SPM fabrication, molecular repositioning or directed self
assembly. This could all be low-temperature processes and it
would allow to go even finer from the current feature sizes of
200nm.

Since the nanotechniques foreseen all have to be from atomic to
less than 100nm one could build complex circuits on the lowest
level CMOS wiring and mix and match elements and even
micromechanics at the first CMOS levels.

After the nanoelectronics being made, a buffer layer of inert
molecules could be add...