Browse Prior Art Database

Method and Apparatus for Computer Debug using Memory Connector

IP.com Disclosure Number: IPCOM000013447D
Original Publication Date: 2000-Sep-01
Included in the Prior Art Database: 2003-Jun-18
Document File: 2 page(s) / 48K

Publishing Venue

IBM

Abstract

The following disclosure relates to a method of debugging computer systems using the memory DIMM connectors and the memory controller as a data path to busses that are not easily probed. As costs decrease in computer systems, more and more sockets are being removed on computer motherboards. In the case of the CPU socket, probing the CPU bus is not possible without special debug probes being directly soldered to the board. Current problem analysis techniques use low frequency "wire-tests". "Wire-tests" are able to test the point to point connections for manufacturing defects but do not cover operating frequency run time faults. The invention disclosed here uses the memory controller sub-system to copy an image of the local bus activity to a memory DIMM connector. Once the image of the system bus activity is available at the memory DIMM connector, conventional analysis techniques such as "logic state analysis" or "signature analysis" may be employed. In many cases a machine will not fail early in Power On Self Test, (POST). During this time a view of the PCI address, (ROM address) and the data returned to the CPU, (System bus) will allow isolation of a fault. Most system designs require buffering between the CPU local data bus (i.e. 60x bus) and the memory data bus. By forcing the direction control logic appropriately, the local bus contents is copied onto the memory data bus. This is done by strapping the appropriate buffer control logic. This is the method currently being used on the Tiger 2 Cost Reduce board where the local bus can not be easily probed, which is useful in debugging the system until the point of the first memory read.

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Method and Apparatus for Computer Debug using Memory Connector

The following disclosure relates to a method of debugging computer systems using the memory DIMM connectors and the memory controller as a data path to busses that are not easily probed.

As costs decrease in computer systems, more and more sockets are being removed on computer motherboards. In the case of the CPU socket, probing the CPU bus is not possible without special debug probes being directly soldered to the board.

Current problem analysis techniques use low frequency "wire-tests". "Wire-tests" are able to test the point to point connections for manufacturing defects but do not cover operating frequency run time faults. The invention disclosed here uses the memory controller sub-system to copy an image of the local bus activity to a memory DIMM connector. Once the image of the system bus activity is available at the memory DIMM connector, conventional analysis techniques such as "logic state analysis" or "signature analysis" may be employed.

In many cases a machine will not fail early in Power On Self Test, (POST). During this time a view of the PCI address, (ROM address) and the data returned to the CPU, (System bus) will allow isolation of a fault. Most system designs require buffering between the CPU local data bus (i.e. 60x bus) and the memory data bus. By forcing the direction control logic appropriately, the local bus contents is copied onto the memory data bus. This is done by strapping the appropriate buffer control logic. This is the method currently being used on the Tiger 2 Cost Reduce board where the local bus can not be easily probed, which is useful in debugging the system until the point of the first memory read.

A further enhancement is to implement miscellaneous logic that could be optionally integrated into the memory controller. This added function allows more local bus cycles to be copied onto the memory bus where the DIMMs reside. By forcing the data buffer direction control signals appropriately, a copy of the local bus memory is copied onto the memory data bus with a 2 clock delay during any transaction except when a memory read is in progress. During a memory read operation, the data being retr...