Browse Prior Art Database

The 630+ Processor Enhanced Implementation of LBIST Diagnostic Logic

IP.com Disclosure Number: IPCOM000013451D
Original Publication Date: 1999-Nov-01
Included in the Prior Art Database: 2003-Jun-18
Document File: 3 page(s) / 36K

Publishing Venue

IBM

Related People

Talal Jaber: AUTHOR

Abstract

This invention describes the implementation of the 630+ Processor Logic Built_in Self_Test(LBIST) diagnostic logic. This logic implementation is capable of detecting and isolating the first fail during LBIST tests and can identify the failing scannable latch(es) within any of the LBIST scan channels. Historically, LBIST tests were implemented as `GO/NOGO' tests. The addition of the LBIST diagnostic logic on the 630+ processor introduced a new debug capability in fault detection and isolation.

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The 630+ Processor Enhanced Implementation of LBIST Diagnostic Logic

This invention describes the implementation of the 630+ Processor Logic
Built_in Self_Test(LBIST) diagnostic logic. This logic implementation is
capable of detecting and isolating the first fail during LBIST tests and can
identify the failing scannable latch(es) within any of the LBIST scan
channels. Historically, LBIST tests were implemented as `GO/NOGO' tests. The
addition of the LBIST diagnostic logic on the 630+ processor introduced a new
debug capability in fault detection and isolation.

      This invention makes use of the STUMPS architecture for a LBIST
implementation on the 630+ processor. It also relies on a on-chip LBIST
controller to provide control of the chip STUMPS configuration, scan and
functional clock generation, initial loading of the LBIST PRPG and MISR as
well as other registers and the final scan out operation of the LBIST scan
channels and the LBIST PRPG, MISR and other LBIST control registers.
The on-chip LBIST controller is JTAG based and can receive instructions over
the JTAG testability bus to control LBIST as well as other test and debug
operations. The on-chip LBIST controller is called COP `Common On-chip
Processor' and has been disclosed in previous publications in the IBM Journal
Of Research And Development, Volume 34, Number 1, January 1990.

      The novelty of this invention is in the introduction of three additional
elements to the control logic of LBIST.

These three elements are described below:

1- The Channel Select Mask Register.

T he Channel Select Mask Register is made up of scan-only latches that can be
loaded and unloaded via instructions sent to the COP by the JTAG bus
controller. The Channel Select Mask Register is a 31 bit wide register. Each
bit in this register corresponds to a LBIST scan channel. If a particular bit
in the CSMR is set to 1, then the corresponding LBIST scan channel data is
inhibited from being compressed into the MISR. The CSMR allows for detection
and isolation of a failing scan channel or a group of scan channels.

2- The LBIST Stop Registe r.

The LSR is a programmable register that can be loaded with a particular stop
value to stop the LBIST test on a particular scan or functional cycle. It is a
30 bit register. Bits 0 through 15 can be programmed to stop on a particular
tester loop. A tester loop is a sequence of LBIST cycles that include the scan
cycles and the functional cycles. To stop on a particular scan cycle, bits 16
through 29 of the LSR can be programmed to stop LBIST on that particular scan
cycle. Bits 16 through 29 of the LSR help identify the failing latch(es)
within a particular LBIST scan channel. Bits 0 through 15 of the LSR help
identify the failing tester loop of an LBIST operation.

3- The Option Register.

The option register is a 16 bit register. Like the CSMR and LSR, it can be
programmed by scanning in data through its scan port via the JTAG testability
bus. Bit 3 of the OR is used to engage or disengage the CSMR and t...