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Browse Prior Art Database

Flexible Hardware Notification Mechanism

IP.com Disclosure Number: IPCOM000013474D
Original Publication Date: 2000-May-01
Included in the Prior Art Database: 2003-Jun-18
Document File: 4 page(s) / 73K

Publishing Venue

IBM

Abstract

A system is disclosed for communicating hardware notifications to firmware, which provides for arbitrary routing of notifications from multiple notifying agents, normally hardware engines, to multiple notified agents, each normally a microprocessor. As well as offering flexibility in the routing of notifications, the content of each notification can be defined by the system designer. The basic elements of the system comprise; a queue for each microprocessor, which collects notifications, pending processing by the associated microprocessor; one or more hardware agents, which each process work requests, and on completion of those work requests post a configured message to a configured address, the address corresponding to one of the aforementioned queues. The preferred embodiment of the queue uses a wrapping buffer located in memory (see Figure 1). It contains multiple elements, each 4 bytes long. Registers define the origin and length of the buffer. For the simplest hardware implementation, the buffer can be chosen from a range of sizes, each a power-of-2 in size, and the origin is chosen to be a whole multiple of the buffer size. A hardware engine manages the enqueueing and dequeueing of entries from the queue. The enqueue side comprises a enqueue pointer register which points to the next free entry, and a port register used to enqueue an entry. At system initialisation, the enqueue pointer register is set to point to the origin of the buffer. The port register is a write-only register, mapped to a fixed address. Any agent may issue a 32bit write to this register. In response to a write, the hardware stores the written value to the current memory location pointed to by the enqueue pointer register, and then advances the enqueue pointer register to refer to the next free entry. When the end of the buffer is reached, the hardware automatically wraps the pointer back to the beginning of the buffer.

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Flexible Hardware Notification Mechanism

A system is disclosed for communicating hardware notifications to firmware, which provides for arbitrary routing of notifications from multiple notifying agents, normally hardware engines, to multiple notified agents, each normally a microprocessor. As well as offering flexibility in the routing of notifications, the content of each notification can be defined by the system designer.

     The basic elements of the system comprise; a queue for each microprocessor, which collects notifications, pending processing by the associated microprocessor; one or more hardware agents, which each process work requests, and on completion of those work requests post a configured message to a configured address, the address corresponding to one of the aforementioned queues.

     The preferred embodiment of the queue uses a wrapping buffer located in memory (see Figure 1). It contains multiple elements, each 4 bytes long. Registers define the origin and length of the buffer. For the simplest hardware implementation, the buffer can be chosen from a range of sizes, each a power-of-2 in size, and the origin is chosen to be a whole multiple of the buffer size.

     A hardware engine manages the enqueueing and dequeueing of entries from the queue. The enqueue side comprises a enqueue pointer register which points to the next free entry, and a port register used to enqueue an entry. At system initialisation, the enqueue pointer register is set to point to the origin of the buffer. The port register is a write-only register, mapped to a fixed address. Any agent may issue a 32bit write to this register. In response to a write, the hardware stores the written value to the current memory location pointed to by the enqueue pointer register, and then advances the enqueue pointer register to refer to the next free entry. When the end of the buffer is reached, the hardware automatically wraps the pointer back to the beginning of the buffer.

     The dequeue side comprises a dequeue pointer register, which points to the next entry which is to be consumed. At initialisation, it is set to point to the origin of the buffer also. The associated microprocessor, under software control, can read the value of the register to obtain the address, then read the indicated location in memory. Having consumed the entry, the microprocessor advances the pointer by adding 4 to the previous address, and then writes the new value to the dequeue pointer register. Hardware records the new pointer value, and when necessary takes care of wrapping the pointer back to the origin of the buffer. The microprocessor can consume more than one entry, by adding some multiple of 4 to the previous address, and storing this back to the dequeue pointer register.

     When the enqueue pointer register points to the same location as the dequeue pointer register, then the buffer is empty. When the enqueue pointer is more advanced than the dequeue pointer, then the buffer contains one...